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Technical Manual
5.6.7. Connector X1100 (Secondary IDE)
All signals are LVTTL compatible.
IDE_D0..15
IDE ATA Data Bus. These are the data pins connected to Secondary Channel.
IDE_A0..2
IDE ATA Address Bus. These are the address pins connected to Secondary Channel.
IDE_CS0#
IDE Chip Select 1 for Secondary Channel 0. This is the Chip Select 1 command output pin to enable the
Secondary IDE device to watch the Read/Write Command.
IDE_CS1#
IDE Chip Select 3 for Secondary Channel 1. This is the Chip Select 3 command output pin to enable the
Secondary IDE device to watch the Read/Write Command.
IDE_DRQ
IDE DMA Request for IDE Master. This is the input pin from the IDE DMA request to do the IDE Master
Transfer. It will active high in DMA or Ultra-33 mode and always be inactive low in PIO mode.
IDE_DACK#
IDE DACK for IDE Master. This is the output pin to grant the IDE DMA request to begin the IDE Master
Transfer in DMA or Ultra-33 mode.
IDE_IORDY
IDE Ready. This is the input pin to indicate the IDE device is ready to terminate the IDE command in
PIO mode. The IDE device can de-assert this input (logic 0) to expand the IDE command if the device is
not ready. In Ultra-33 mode, this pin has different functions.
IDE_IOR#
IDE IOR Command. This is the IOR command output pin to notify the IDE device to assert the Read
Data in PIO and DMA mode. In Ultra-33 mode, this pin has different functions.
IDE_IOW#
IDE IOW Command. This is the IOW command output pin to notify the IDE device that the available
Write Data is already asserted by IDE Busmaster in PIO and DMA mode. In Ultra-33 mode, this pin is
driven by IDE Busmaster to force IDE device to terminate current transaction.
DIAG_P
Output by the drive if it is jumpered in the slave mode; input to the drive if it is jumpered in the master
mode. The signal indicates to a master that the slave has passed its internal diagnostic command. Ne-
cessary for using IDE master/slave-mode on Secondary IDE Channel.
IDE_SEL
IDE Cable Select. Used to configure this device as a Master or a Slave. When the pin is grounded, this
device is configured as a Master. When the pin is open, this device is configured as a Slave.
IDE_RST#
Low active hardware reset.
IDE_IRQ
IDE Channel interrupt signal.
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Page 23 of 71 Pages
Version 1.04
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