Table of Contents
Advertisement
•
Component Data Width: Specifies the bit width of input samples. This is used in
conjunction with the Video Format to determine the width of the input video bus,
vid_data, and the AXI4-Stream data bus, m_axis_video_tdata.
•
Video Format: Specifies the video format used. The video formats are specified in the
Video IP: AXI Feature Adoption section of the
The format selected determines the number of components used. The number of
components (1-4) is multiplied by the component width to determine the width of the
video data bus, v_data. In turn, this width is rounded up to the nearest factor of 8 to
determine the width of the AXI4-Stream data bus, m_axis_video_tdata. For
example, if the component width is 14 and the Video Format is RGB (3 components),
the v_data will be 42 bits wide and m_axis_video_tdata will be 48 bits.
•
FIFO Depth: Specifies the number of locations in the input FIFO. The options for FIFO
depth are 32, 1024, 2048, 4096, and 8192.
•
Hysteresis Level: Defines the "Cushion" level of the frame buffer. i.e. the number of
locations that are considered the minimum fill level for FIFO operation to start. This
number must be at least 16 less than the depth of the FIFO.
Video In to AXI4-Stream
PG043 April 24, 2012
UG761 AXI Reference Guide.
www.xilinx.com
Graphical User Interface (GUI)
17
Advertisement
Table of Contents
