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Table 2-7: Port Name I/O Width Description
Signal Name
empty
axis_enable
Video Timing Pass-Through Outputs
Table 2-8: Port Name I/O Width Description
Signal Name
vtd_vsync
vtd_hsync
vtd_vblank
vtd_hblank
vtd_active_video
Video Input Interface
The Video In to AXI4-Stream core receives standard video data using the Video Input
interface and transmits data using AXI4-Stream interfaces that implement a video protocol
as defined in the AXI Reference Guide (UG761), Video IP: AXI Feature Adoption section.
Table 2-9: Port Name I/O Width Description
Signal Name
vid_in_clk
video_de
vid_vsync
vid_hsync
vid_vblank
vid_hblank
video_data
Video In to AXI4-Stream
PG043 April 24, 2012
Direction Width
Active HIGH FIFO empty flag.
1 = FIFO read was attempted when FIFO was empty.
Out
1
Due to EOL flushing, this flag will be asserted at the end of every
line during normal operation.
Enable the AXI4-Stream bus.
1 = Enable AXI4-Stream bus to operate.
In
1
0 = Inhibit AXI4-Stream operation by forcing m_axis_video_tdata
LOW.
Direction Width
Vertical synch video timing signal.
Out
1
Out
1
Horizontal synch video timing signal.
Out
1
Vertical blank video timing signal.
Horizontal blank video timing signal.
Out
1
Out
1
Active video flag.
1 = active video, 0 = blanked video
Direction
Width
In
1
In
1
In
1
In
1
In
1
In
1
In
8-64
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Core Interfaces and Register Space
Description
Description
Description
Video input clock
Video data enable.
1 = active video, 0 = blanked video
Vertical synch video timing signal. Active High
Horizontal synch video timing signal. Active High
Vertical blank video timing signal. Active High
Horizontal blank video timing signal. Active High
Parallel video input data.
12
Product Specification
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