Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual page 14

the MSB to form a N*8-bit wide vector before connecting to m_axis_video_tdata.
Padding does not affect the size of the core.
Similarly, data on the Video in to AXI-4 Stream output m_axis_video_tdata is packed
and padded to multiples of 8 bits as necessary.
12-bit RGB data. Zero padding the most significant bits is only necessary for 10, 12, and 14
bit wide data.
X-Ref Target - Figure 2-2
READY/VALID Handshake
A valid transfer occurs whenever READY, VALID, ACLKEN, and ARESETn are high at the
rising edge of ACLK. During valid transfers, DATA only carries active video data. Blank
periods and ancillary data packets are not transferred via the AXI4-Stream Video protocol.
Guidelines on Driving m_axis_video_tready
The m_axis_video_tready signal may be asserted before, during or after the cycle in
which the Video in to AXI4-Stream core asserted m_axis_video_tvalid. The assertion of
m_axis_video_tready may be dependent on the value of m_axis_video_tvalid. A slave
that can immediately accept data qualified by m_axis_video_tvalid, should pre-assert
its m_axis_video_tready signal until data is received. Alternatively,
m_axis_video_tready can be registered and driven the cycle following VALID
assertion. It is recommended that the AXI4-Stream slave should drive READY
independently, or pre-assert READY to minimize latency.
Start of Frame Signal - m_axis_video_tuser
The Start-Of-Frame (SOF) signal, physically transmitted over the AXI4-Stream tuser0
signal, marks the first pixel of a video frame. The SOF pulse is 1 valid transaction wide, and
must coincide with the first pixel of the frame. SOF serves as a frame synchronization signal,
which allows downstream cores to re-initialize, and detect the first pixel of a frame. The SOF
signal may be asserted an arbitrary number of aclk cycles before the first pixel value is
presented on tdata, as long as a tvalid is not asserted.
End of Line Signal - m_axis_video_tlast
The End-Of-Line signal, physically transmitted over the AXI4-Stream tlast signal, marks
the last pixel of a line. The EOL pulse is 1 valid transaction wide, and must coincide with the
last pixel of a scan-line, as seen in
Video In to AXI4-Stream
PG043 April 24, 2012
Figure 2-2: RGB Data Encoding on m_axis_video_tdata
Figure
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Core Interfaces and Register Space
Figure 2-10 shows an example of this for
2-3.
14
Product Specification