Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual page 21

Data Formatter
The data formatter derives the EOL and SOF flags required to transmit AXI4-Stream Video
protocol. It also controls writing of the FIFO in the stream coupler. The flags are generated
by looking at the edges of the data enable (DE) signal. Since only active pixels are carried on
AXI4-Stream, the FIFO is only written when active pixels are present. There are input
registers on all inputs to minimize input loading. The EOL flag is timed to be coincident with
the last pixel before the falling edge of DE. Video data is delayed so that the falling edge of
DE can be detected, and the EOL flag asserted coincident with the proper pixel as it is
written to the FIFO. Similarly, the SOF flag is created based on the rising edge of DE,
however it additionally requires knowledge of the vertical timing to identify the first line.
This is done using the logical or OR vsync and vblank. The falling edge of either of these
indicates that the input video is in the vertical blanking period. This enables SOF
generation, and the SOF flag is asserted at the next rising edge of DE; the first valid pixel of
the field.
The rising edge of DE also resets the vertical blanking flip-flop.
of outputs and internal signals relative to the inputs. The de_1 and de_2 signals are delayed
versions of de. The outputs are highlighted in bold.
X-Ref Target - Figure 4-2
Stream Coupler
The Stream Coupler block consists mainly of an asynchronous FIFO and write logic for the
input side of the FIFO. Reading of the FIFO is controlled by the Output Synchronizer. The
FIFO serves two primary purposes:
1. Clock domain crossing
2. Buffering of data between AXI4-Stream input and video output.
Video In to AXI4-Stream
PG043 April 24, 2012
Figure 4-2: Data Formatter Timing Diagram
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Module Descriptions
Figure 4-2 shows the timing
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