Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual page 24

X-Ref Target - Figure 4-4
Figure 4-4: Synchronization and Handshaking for Clock Domain Crossing of Pointers
The extra delay for turning around the handshaking signal insures that data will be
transferred reliably no matter what the relative clock rates. i.e. if Freqa > 2Freqb each "req"is
still guaranteed to update the sync pointer in domain B. By the same token, if Freqb >
2Freqa, each ack is guaranteed to update the pointer sample in domain A.
an example of pointer synchronization between clock domains, and the handshaking
scheme shown in
acknowledge. The "request" state is when Req and Ack are not equal and "acknowledge" is
when they are equal.
X-Ref Target - Figure 4-5
Figure 4-5: Waveform Diagram of Handshaking and Clock Domain Crossing of Pointers
This sample and hold method with handshaking delays the capture of the pointers by
several clock edges in each domain but the pointer transfers are always reliable and glitch
free. The latency of the pointers causes pessimism in the level outputs, and the flags. That
is, the empty flag will persist in the read domain for several clocks after a write has
occurred, etc. Also, the level output will not necessarily be monotonic. This is taken into
Video In to AXI4-Stream
PG043 April 24, 2012
Figure 4-4. This handshaking scheme, utilizes two states: request and
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Module Descriptions
Figure 4-5 shows
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