Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual page 23

X-Ref Target - Figure 4-3
Figure 4-3: Block Diagram of Bridge Core Asynchronous FIFO
Synchronized Gray codes are commonly used in asynchronous FIFOs to eliminate the
problems of synchronizing multiple counter bits changing on the same clock edge.
However, instead of Gray code pointers, the FIFO for the Video In to AXI4-Stream core uses
binary pointers synchronized via handshaking. The main reason is that calculating the fill
level, which is used integrally in the read logic, is simple with binary pointers but impractical
with gray code pointers.
Clock Domain Crossing of Pointers
The synchronization and handshaking for pointers is shown in detail in
two register delays are required to resolve metastability. The third is to insure that the
register has time to take the data before the handshaking is returned. Otherwise if the clock
in one domain were several times faster than the other, there is a chance that the
handshaking could be returned, before the pointer register is updated in the slower clock
domain.
Video In to AXI4-Stream
PG043 April 24, 2012
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Module Descriptions
Figure 4-4. The first
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