Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual page 19

X-Ref Target - Figure 4-1
Figure 4-1: Example of ACLK Routing and AXI4-Stream Interconnect
Clocking
There are two clocks used in this core.
• Video input pixel clock
• AXI4-Stream clock
The video input clock corresponds to the video line standard used on the input. It is part of
the video line standard and is used by both the Video In to AXI4-Stream core and by the
corresponding Video Timing Controller core that is used to detect video timing.
The AXI4-Stream clock (aclk) is part of the AXI4-Stream bus. To minimize buffering
requirements, this clock should be of equal or higher frequency than the video input clock.
This clock can be slower than the video input clock, in which case, additional buffering is
required to store pixels so that lines can be input at the burst rate of the video clock. This
is discussed in the
higher than the average pixel rate.
Resets
There are two external resets provided: rst, which resets the entire core, and aresetn, which
resets the AXI4-Stream interface. Both resets cause the FIFO to be reset. When asserted, the
reset should be held for least two clock periods of the lowest frequency clock.
Video In to AXI4-Stream
PG043 April 24, 2012
Buffer Requirements section. At a minimum, the aclk frequency must be
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General Design Guidelines
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