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AXI4-Stream Interface
AXI4-Stream Signal Names and Descriptions
Table 2-10
describes the AXI4-Stream signal names and descriptions.
Table 2-10: AXI4-Stream Data Interface Signal Descriptions
Signal Name
m_axis_video_tdata
m_axis_video_tvalid
m_axis_video_tready
m_axis_video_tuser
m_axis_video_tlast
ACLK
ACLKEN
ARESETn
The ACLK, ACLKEN and ARESETn signals are shared between the core, the AXI4-Stream
data interfaces, and AXI4-Lite control interfaces in the system.
ACLK
The AXI4-Stream must be synchronous to the clock signal ACLK. AXI4-Stream signals are
sampled on the rising edge of ACLK. AXI4-Stream output signal changes occur after the
rising edge of ACLK.
ACLKEN
The ACLKEN pin is an active-high, synchronous clock-enable input pertaining the
AXI4-Stream interface. Setting ACLKEN low (de-asserted) halts the operation of the
AXI4-Stream Bus despite rising edges on the ACLK pin. Internal states are maintained, and
output signal levels are held until ACLKEN is asserted again. When ACLKEN is de-asserted,
core AXI4-Stream inputs are not sampled, except ARESETn, which supersedes ACLKEN.
ARESETn
The ARESETn pin is an active-low, synchronous reset input. ARESETn supersedes ACLKEN,
and when set to 0, the core resets even if ACLKEN is de-asserted.
Video Data
The AXI4-Stream interface specification restricts TDATA widths to integer multiples of
8 bits. Therefore, in the case of data with 10 or 12 bits, data must be padded with zeros on
Video In to AXI4-Stream
PG043 April 24, 2012
Direction
Width
Out
8 to 64
Out
1
In
1
Out
1
Out
1
In
1
In
1
In
1
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Core Interfaces and Register Space
Description
Output Video Data
Output Valid
Output Ready
Output Video Start Of Frame
Output Video End Of Line
Clock
Clock Enable
Active low synchronous
Product Specification
13
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