Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual page 4

Introduction
The Xilinx LogiCORE™ IP Video In to
AXI4-Stream core is designed to interface from
a video source (clocked parallel video data with
synchronization signals - active video with
either syncs, blanks or both) to the AXI4-Stream
Video Protocol Interface. This core works in
conjunction with the timing detector portion of
the Xilinx Video Timing Controller (VTC) core.
This core provides a bridge between a video
input and video processing cores with
AXI4-Stream Video Protocol interfaces.
Features
• Video (clocked parallel video data with
synchronization signals - active video with
either syncs, blanks or both) input
• AXI4-Stream Video Protocol interface for
output
• Interface to Xilinx Video Timing Controller
core for video timing generation
• Handles asynchronous clock boundary
crossing between video clock domain and
AXI4-Stream clock domain
• Selectable FIFO depth from 64 -8192
locations
• Selectable input data width of 8-64 bits
Video In to AXI4-Streamt
PG043 April 24, 2012
LogiCORE IP Video In to
LogiCORE IP Facts Table
Supported
(1)
Device Family
Supported User
Interfaces
Resources
Documentation
Design Files
Example Design
Test Bench
Constraints File
Simulation
Models
Design Entry
Tools
(3)
Simulation
Synthesis Tools
1. For a complete listing of supported devices, see the
notes for this core.
2. Video protocol as defined in the Video IP: AXI Feature
Adoption section of
3. For the supported versions of the tools, see the
Suite 14: Release Notes
www.xilinx.com
AXI4-Stream v1.0
Core Specifics
®
Zynq-7000, Artix-7, Virtex -7, Kintex
Virtex-6, Spartan
AXI4-Stream
Provided with Core
Product Guide
Verilog Source Code
Verilog Source Code
Tested Design Tools
Mentor Graphics ModelSim, Xilinx ® ISim
Xilinx Synthesis Technology (XST)
Support
Provided by Xilinx, Inc.
UG761 AXI Reference Guide.
Guide.
Product Specification
®
-7,
®
-6
(2)
See Table 2-1.
Not Provided
Not Provided
Not Provided
ISE 14.1
release
ISE Design
4