Clock Error (Bit 3); Overflow (Bit 1); Underflow (Bit 0); Status Mask - Address 0Eh - Cirrus Logic CS5346 Manual

7.10.1 Clock Error (Bit 3)

Function:
Indicates the occurrence of a clock error condition.

7.10.2 Overflow (Bit 1)

Function:
Indicates the occurrence of an ADC overflow condition.

7.10.3 Underflow (Bit 0)

Function:
Indicates the occurrence of an ADC underflow condition.
7.11

Status Mask - Address 0Eh

7 6
Reserved Reserved
Function:
The bits of this register serve as a mask for the Status sources found in the register
on page 32. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status
register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status
register. The bit positions align with the corresponding bits in the Status register.
7.12

Status Mode MSB - Address 0Fh

7.13

Status Mode LSB - Address 10h

7 6
Reserved Reserved
Reserved Reserved
Function:
The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to
update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the sta-
tus bit becomes active on the arrival of the condition. In the Falling-Edge Active Mode, the status bit be-
comes active on the removal of th e condition. In L evel-Active Mode, the status bit is active during the
condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
DS861PP3
5 4
Reserved Reserved
5 4
Reserved Reserved
Reserved Reserved
3 2
ClkErrM Reserved
3 2
ClkErr1 Reserved
ClkErr0 Reserved
CS5346
1 0
OvflM UndrflM
"Status - Address 0Dh"
1 0
Ovfl1 Undrfl1
Ovfl0 Undrfl0
33