Master Mode; Slave Mode; High-Pass Filter And Dc Offset Calibration; Figure 8.Master Mode Clocking - Cirrus Logic CS5346 Manual

5.2.2

Master Mode

As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in
5.2.3

Slave Mode

In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x or 48x Fs, depending on the desired speed mode. Refer to
SCLK/LRCK Ratio
5.3

High-Pass Filter and DC Offset Calibration

When using operational amplifiers in the input circuitry driving the CS5346, a small DC offset may be driven
into the A/D converter. The CS5346 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a D C level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset fro m the output of the decimation
filter. If the HPFFreeze bit (See
the current value of the DC offset for the each channel is frozen and this DC offset will continue to be sub-
tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS5346 with the high-pass filter enabled until the filter settles. See the Digital Filter Char-
acteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5346.
20
MCLK Freq Bits
000
÷1
÷1.5 001
MCLK ÷2 010
011
÷3
÷4 100
Figure 8. Master Mode Clocking
Single-Speed
48x, 64x, 128x

Table 3. Slave Mode Serial Bit Clock Ratios

"High-Pass Filter Freeze (Bit 1)" on page
Figure
÷256 00
÷128 01
LRCK
÷64 10
FM Bits
÷4 00
÷2
01 SCLK
÷1 10
Table 3
Double-Speed
48x, 64x
29.) is set during normal operation,
CS5346
8.
for required clock ratios.
Quad-Speed
48x, 64x
DS861PP3