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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic '0' = DGND = AGND = 0 V; Logic '1' = VLS, C
Sample Rate
MCLK Specifications
MCLK Frequency
MCLK Input Pulse Width High/Low
Master Mode
LRCK Duty Cycle
SCLK Duty Cycle
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
Slave Mode
LRCK Duty Cycle
SCLK Period
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
12. See
Figure 1
14
Parameter
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
and
Figure 2 on page
= 20 pF.
(Note 12)
L
Symbol
Fs
Fs
Fs
f
mclk
t
clkhl
t
slr
t
sdo
t
sclkw
t
sclkw
t
sclkw
t
sclkh
t
sclkl
t
slr
t
sdo
15.
Min
Typ
8
-
50
-
100
-
2.048
-
8
-
-
50
-
50
-10
-
0
-
40
50
9
10
-------------------- -
-
Fs
128
9
10
----------------- -
-
Fs
64
9
10
----------------- -
-
Fs
64
30
-
48
-
-10
-
0
-
CS5346
Max
Unit
50
kHz
100
kHz
200
kHz
51.200
MHz
-
ns
-
%
-
%
10
ns
36
ns
60
%
-
ns
-
ns
-
ns
-
ns
-
ns
10
ns
36
ns
DS861PP3
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