Adc Control - Address 04H; Functional Mode (Bits 7:6); Digital Interface Format (Bit 4); Mute (Bit 2) - Cirrus Logic CS5346 Manual

7.3

ADC Control - Address 04h

7 6
FM1 FM0
7.3.1

Functional Mode (Bits 7:6)

Function:
Selects the required range of sample rates.
FM1
0
0
1
1
7.3.2

Digital Interface Format (Bit 4)

Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format
bit. The options are detailed in
DIF
0
1
7.3.3

Mute (Bit 2)

Function:
When this bit is set, the serial audio output of the both channels is muted.
7.3.4

High-Pass Filter Freeze (Bit 1)

Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See
page 20.
7.3.5

Master / Slave Mode (Bit 0)

Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
DS861PP3
5 4
Reserved DIF
FM0
0 Single-Speed Mode: 8 to 50 kHz sample rates
1 Double-Speed Mode: 50 to 100 kHz sample rates
0 Quad-Speed Mode: 100 to 200 kHz sample rates
1 Reserved

Table 6. Functional Mode Selection

Table 7 and may be seen in
Description
Left-Justified (default)
I²S

Table 7. Digital Interface Formats

3 2
Reserved Mute
Mode
Figure 3 and Figure
Format
0
1
"High-Pass Filter and DC Offset Calibration" on
CS5346
1 0
HPFFreeze M/S
4.
Figure
3
4
29