LRCK
SCLK
SDATA
MSB
-1
-2
-3
LRCK
SCLK
SDATA
MSB
-1
-2
-3
DS861PP3
LRCK
Input
t
slr
SCLK
Input
t
sdo
SDOUT
Figure 1. Master Mode Serial Audio Port Timing
LRCK
Output
t
slr
SCLK
Output
t
sdo
SDOUT
Figure 2. Slave Mode Serial Audio Port Timing
Channel A - Left
+5 +4
+3 +2 +1
-4
-5
LSB
Figure 3. Format 0, 24-Bit Data Left-Justified
Channel A - Left
-4
-5
+5 +4
+3 +2 +1
LSB
Figure 4. Format 1, 24-Bit Data I²S
t
t
sclkh
sclkl
t
sclkw
Channel B - Right
+5 +4
+3
MSB
-1
-2
-3
-4
Channel B - Right
MSB
-1
-2
-3
-4
+5 +4
+3 +2 +1
CS5346
+2 +1
LSB
LSB
15
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