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6. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr
Function
01h
Chip ID
PART3
pg. 28
02h
Power Control
Freeze
pg. 28
03h
Reserved
Reserved Reserved Reserved Reserved
04h
ADC Control
pg. 29
05h
MCLK
Reserved
Frequency
pg. 30
06h
PGAOut
Reserved
Control
pg. 30
07h
PGA Ch B
Reserved Reserved
Gain Control
pg. 30
08h
PGA Ch A
Reserved Reserved
Gain Control
pg. 31
09h
Analog Input
Reserved Reserved Reserved
Control
pg. 31
0Ah -
Reserved
Reserved Reserved Reserved Reserved
0Bh
0Ch Active Level
Reserved Reserved Reserved Reserved
Control
pg. 32
0Dh Interrupt Status Reserved Reserved Reserved Reserved
pg. 32
0Eh Interrupt Mask
Reserved Reserved Reserved Reserved
pg. 33
0Fh
Interrupt Mode
Reserved Reserved Reserved Reserved
MSB
pg. 33
10h
Interrupt Mode
Reserved Reserved Reserved Reserved
LSB
pg. 33
DS861PP3
7
6
5
PART2
PART1
1
1
0
Reserved Reserved Reserved
0
0
0
0
0
0
FM1
FM0
Reserved
0
0
0
MCLK
MCLK
Freq2
Freq1
0
0
0
PGAOut
Reserved Reserved
0
1
0
Gain5
0
0
0
Gain5
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
PART0
REV3
0
x
PDN_MIC
PDN_ADC
0
0
Reserved
Reserved
0
1
DIF
Reserved
0
0
MCLK
Reserved
Reserved
Freq0
0
0
Reserved
Reserved
0
0
Gain4
Gain3
0
0
Gain4
Gain3
0
0
PGASoft
PGAZero
1
1
Reserved
Reserved
0
0
Reserved
Reserved
0
0
ClkErr
Reserved
0
0
ClkErrM
Reserved
0
0
ClkErr1
Reserved
0
0
ClkErr0
Reserved
0
0
CS5346
2
1
REV2
REV1
x
x
Reserved
0
0
Reserved
Reserved
0
0
Mute
HPFFreeze
0
0
Reserved
Reserved
0
0
Reserved
Reserved
0
0
Gain2
Gain1
0
0
Gain2
Gain1
0
0
Sel2
Sel1
0
0
Reserved
Reserved
0
0
Reserved
Active_H/L
0
0
Ovfl
0
0
OvflM
UndrflM
0
0
Ovfl1
Undrfl1
0
0
Ovfl0
Undrfl0
0
0
0
REV0
x
PDN
1
0
M/S
0
0
0
Gain0
0
Gain0
0
Sel0
1
0
0
Undrfl
0
0
0
0
27
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