Mclk Frequency - Address 05H; Master Clock Dividers (Bits 6:4); Pgaout Control - Address 06H; Pgaout Source Select (Bit 6) - Cirrus Logic CS5346 Manual

7.4

MCLK Frequency - Address 05h

7 6
MCLK
Reserved
Freq2
7.4.1

Master Clock Dividers (Bits 6:4)

Function:
Sets the frequency of the supplied MCLK signal. See
7.5

PGAOut Control - Address 06h

7 6
Reserved PGAOut
7.5.1

PGAOut Source Select (Bit 6)

Function:
This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to
Table 9.
7.6

Channel B PGA Control - Address 07h

7 6
Reserved Reserved
7.6.1

Channel B PGA Gain (Bits 5:0)

Function:
See "Channel A PGA Gain (Bits 5:0)" on page 31.
30
5
MCLK MCLK
Freq1 Freq0
MCLK Divider MCLK Freq2
÷ 1
÷ 1.5
÷ 2
÷ 3
÷ 4
Reserved
Reserved

Table 8. MCLK Frequency

5
Reserved Reserved
PGAOut
0
1

Table 9. PGAOut Source Selection

5
Gain5 Gain4
4 3
Reserved
Table 8 for the appropriate settings.
MCLK Freq1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
4 3
Reserved
PGAOutA & PGAOutB
High Impedance
PGA Output
4 3
Gain3
2 1
Reserved Reserved
MCLK Freq0
0
1
0
1
0
1
x
2 1
Reserved Reserved
2 1
Gain2 Gain1
CS5346
0
Reserved
0
Reserved
0
Gain0
DS861PP3