Figure 13.Master Mode Clocking; Table 3. Master Mode Left Justified And I²S Clock Ratios; Table 4. Slave Mode Left Justified And I²S Clock Ratios; Table 5. Slave Mode Tdm Clock Ratios - Cirrus Logic CS4244 Manual

4.4.2 Master Mode Clock Ratios
As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK
is equal to F
S
Mode.
The resulting valid master mode clock ratios are shown in
MCLK/F
S
SCLK/F
S
4.4.3 Slave Mode Clock Ratios
In Slave Mode, SCLK and FS/LRCK operate as inputs. The FS/LRCK clock frequency must be equal to
the sample rate, F
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
512x, 256x, 128x, 64x, 48x or 32x F
and Table 5 for required clock ratios.
MCLK/F
S
SCLK/F
S
(Note 34)
MCLK/F
S
SCLK/F
S
Note:
34. For all cases, the SCLK frequency must be less than or equal to the MCLK frequency.
DS900F2
and SCLK is equal to 64x F
MCLK Rate Bits
MCLK ÷1.5
÷1
Figure 13. Master Mode Clocking
Table 3. Master Mode Left Justified and I²S Clock Ratios
, and must be synchronously derived from the supplied master clock, MCLK.
S
, depending on the desired format and speed mode. Refer to
S
Table 4. Slave Mode Left Justified and I²S Clock Ratios
256x, 384x, 512x

Table 5. Slave Mode TDM Clock Ratios

as shown in Figure 13. TDM format is not supported in Master
S
÷512
÷256
x2 000
x2 001 Speed Mode Bits
010
÷8
PLL active ÷4
Table 3
SSM
256x, 384x, 512x
64x
SSM
256x, 384x, 512x
32x, 48x, 64x, 128x
SSM
256x
00
FS/LRCK
01
00
SCLK
01
below.
DSM
128x, 192x, 256x
64x
DSM
128x, 192x, 256x
32x, 48x, 64x
512x
512x
CS4244
Table 4
DSM
256x
256x
27