Table 4-8 Interrupt Mapping - SMART Embedded Computing ATCA-F125 Assembly, Installation And Use

The interrupt controller provides interrupt management, and is responsible for receiving
hardware-generated interrupts from different sources (both internal and external),
prioritizing them, and delivering them to the CPU for servicing. The PIC is set to the mixed
mode on ATCA-F125 so that both internal and external interrupts are delivered using
normal priority and delivery mechanisms.
Some interrupt sources are collected by the onboard FPGA. This FPGA includes an
interrupt source register, which reflects the actual interrupt status. The interrupt inputs of
the FPGA are mapped to the IRQ[11:0] signals, which are connected to the P2020 QorIQ
Integrated Processor.
Table 4-8
Interrupt Source
BCM56334
BITS Framer 1
DS26503
BITS Framer 2
DS26503
DIMMs
88SE6121 SATA
RTM FPGA
FPGA UART
IPMC LPC
Watchdog Timer
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94P)
Interrupt Mapping
Port Signal
INTA
INT_L
INT_L
EVENT_L
INTA
INT_L
UART_INT
SERIRQ_IN
TOUT
1st stage
WDT
Source
P2020 PCIE 1
Internal
INTA
BITS1_INT_L Direct
BITS2_INT_L Direct
DIMM_EVENT_L Direct
P2020 PCI2 INTA Internal
RTM_INT_L Direct
FPGA
SP_IRQ_6
(ORed)
Functional Description
Type
Active Low OD
Active Low OD
Active Low OD
Active Low LVTTL
Active Low LVTTL
P2020
IRQ
0
1
2
3
4
5
6
97