Bcm5709S Dual Gigabit Ethernet Mac/Phy; Table 4-6 Amc Bay Port Assignments - SMART Embedded Computing ATCA-F125 Assembly, Installation And Use

Functional Description
Table 4-6
Connector
Region
Clocking
Common Options
Fat Pipes
Extended Options
4.10.1

BCM5709S Dual Gigabit Ethernet MAC/PHY

The Broadcom BCM5709S is a PCI Express based single-chip dual Gigabit Ethernet MAC
controller with integrated PHY and SerDes cores. This device supports a 4x PCI Express
v1.1/v2.0 compliant interface to the host processor in the AMC bay. The dual MAC/PHY
supports either 1Gb SERDES or triple speed copper interfaces. This device will be
configured to use the SERDES interfaces. Controller 0 is routed to the AMC-Base cross
connect mux. Controller 1 is routed to the AMC-Fabric cross connect mux.
88
AMC Bay Port Assignments
Port No. PrAMC Usage
1 TCLKA
2 TCLKB
3 TCLKC
4 TCLKD
5 FCLKA
0 Gigabit Ethernet Link 0
1 Gigabit Ethernet Link 1
2 SATA Link 0
3 SATA Link 1
4 PCI-Express Lane 0
5 PCI-Express Lane 1
6 PCI-Express Lane 2
7 PCI-Express Lane 3
8 PCIE/XAUI/SGMII
9 PCIE/XAUI/SGMII
10 PCIE/XAUI/SGMII
11 PCIE/XAUI/SGMII
12 Unused
13-20 Unused
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94P)
Functional Description
ATCA-F125 Source/Target
From FPGA Telecom Clock logic
From FPGA Telecom Clock logic
From FPGA Telecom Clock logic
From FPGA Telecom Clock logic
From PCIE 100 MHz differential
clock distribution
To BCM56334
To BCM56820 using mux
To SATA HDD Mux
Unused
To BCM5709S x4 PCIE
To RTM or FIX XAUI or FIX SGMII
To RTM or FIX XAUI
Unused
Unused