Service Processor Core Reset Domain; 4.12.1.1 Service Processor; Table 4-7 Reset Signals - SMART Embedded Computing ATCA-F125 Assembly, Installation And Use

Functional Description
A software controlled reset register within the FPGA will provide software controlled resets
to the FIX, BIX and PHY functions. The FPGA will also implement a last reset register to
capture the source of the last reset generated on the board.
Table 4-7
Reset Source
BOARD_PWR_OK
PAYLOAD_RST_L
FRONT_PANEL_RST_L
HRST_REQ_L
COP_HRESET_L
COP_SRESET_L
AMC_EN
AMC_PWR_GOOD
Software Control in FPGA No
4.12.1

Service Processor Core Reset Domain

The service processor core includes the P2020 QorIQ Integrated Processor, its memory
and the on-board resources attached to the local bus.

4.12.1.1 Service Processor

The hard reset signal HRST_L causes the P2020 QorIQ Integrated Processor to abort all
current internal and external transactions and set all registers to their default values.
HRST_L may be asserted at any time completely asynchronously. HRST_L needs to be
asserted during power-on reset. During HRST_L assertion, the configuration input signals
are sampled into registers inside the P2020 QorIQ Integrated Processor.
94
Reset Signals
Yes No
Yes No
Yes No
Yes No
Yes No
No Yes
No No
No No
No
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94P)
Yes Yes Yes Yes
Yes Yes Yes Yes
Yes Yes Yes Yes
No No No No
Yes Yes Yes Yes
No No No No
No No No No
No No No No
Yes Yes Yes Yes
Functional Description
Yes Yes No Yes
Yes Yes No Yes
Yes Yes No Yes
No No No No
Yes Yes No Yes
No No No No
No No Yes No
No No Yes No
Yes Yes No Yes
Yes
No
No
No
No
No
No
No
No