Figure 7-1. Adc12Dj5200Rfevm Clocking System Block - Texas Instruments ADC DJ 00RF Series User Manual

HSDC Pro Settings for Optional ADC Device Configuration
7.2.1 External Clocking Option (Default)
By default, the EVM is configured to use the external clock option. The user provide and external clock signal for
both the ADC sampling clock(DEVCLK at J10) and also the Reference clock(REF CLK at J17) which feed into
the LMK04828 and is used in clock distribution mode and provides the FPGA reference clock, FPGA SYSREF
signal and ADC SYSREF signal. If coherent sampling is desired the external clocking has to be used.
shows the block diagram of external clocking option:
The EVM can be configured to use external clocks with the following steps (see
1. Modify the hardware:
a. Remove R171 and R174, populate C2 and C3.
b. Remove C52 and C306, populate C60 and C61
c. Install Jumper J13
LMK00304
REFCLK
(J17)
260 MHz
LMK61E2
SYSREF
32.5 MHz
External Clock
Figure 7-1. ADC12DJ5200RFEVM Clocking System Block Diagram
18 ADCxxDJxx00RF Evaluation Module
OSCIN
LMK04828
SDCLKx SYNC
SDCLKx SYSREFREQ
CLKIN0
SDCLKx
SDCLKx
/N
CLKIN1 DCLKx
Copyright © 2021 Texas Instruments Incorporated
Figure
REFCLK
(J10)
5200 MHz
ADC12DJ5200RF
LMX2594
SYNC
RFOUTA CLK
DA[15:0]
RFOUTB SYSREF
SLAU640A – APRIL 2019 – REVISED JUNE 2021
www.ti.com
Figure 7-1
7-4):
Board SYNC
FMC
SYNC
DA[15:0]
FPGA_SYSREF
FPGA_CLK[3:0]
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