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Ensure the power connections to the EVMs are the correct polarity. Failure to do so may
result in immediate damage.
Leave the power switches in the off position until directed later.
3.5 Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed)
Connect a signal generator to the VIN input of the ADC12DJ5200RFEVM through a bandpass filter and
attenuator at the SMA connector. This must be a low-noise signal generator. TI recommends a Trilithic-tunable
bandpass filter to filter the signal from the generator. Configure the signal generator for 2897 MHz, 6 dBm.
When External Clocking is Used
1. Connect a signal generator to the DEVCLK input of the EVM through a bandpass filter. This signal generator
must be a low-noise signal generator. TI recommends a Trilithic-tunable bandpass filter to filter the signal
coming from the generator. Configure the signal generator for the desired clock frequency in the range of
0.8 to 5.2 GHz. For best performance when using an RF signal generator, the power input to the CLK SMA
connector must be 10 dBm (2.0 Vpp into 50 Ω). The signal generator must increase above 10 dBm by
an amount equal to any additional attenuation in the clock signal path, such as the insertion loss of the
bandpass filter. For example, if the filter insertion loss is 2 dB, the signal generator must be set to 10 dBm +
2 dB = 12 dBm.
1. Connect a signal generator to the reference signal input of the EVM at REF CLK(J17). Configure the signal
generator for the desired (260MHz) clock frequency. Set the output power to approximately 6–9 dBm.
a. The Reference clock frequency can be obtained from the ADC12DJ5200RFEVM GUI. Once
the ADC12DJ5200EVM GUI is configured to the desired JMODE mode and clock rate. The
Reference Clock frequency required by the EVM is displayed on first page of the GUI shown
with red square in
b. Ensure that the DEVCLK and Reference clock sources are frequency-locked using a common
10-MHz reference to ensure functionality. Frequency locking the input signal generator to the
other generators can also be done if coherent sampling is desired.
c. Do not turn on the RF output of any signal generator at this time.
d. When using the ADC in single-input mode, the device uses both edges of DEVCLK for
sampling.
3.6 Turn On the TSW14J57EVM Power and Connect to the PC
1. Turn on the power switch of the TSW14J57EVM.
2. Connect a mini-USB cable from the PC to the TSW14J57EVM.
3. If this is the first time connecting the TSW14J57EVM to the PC, follow the on-screen instructions to
automatically install the device drivers. See the
3.7 Turn On the ADC12DJ5200RFEVM Power Supplies and Connect to the PC
1. Turn on the 12-V power supply to power up the EVM.
2. Connect the EVM to the PC with the mini-USB cable.
3.8 Turn On the Signal Generator RF Outputs
Turn on the RF signal output of the signal generator connected to VIN. If external clocking is used, turn on the
RF signal outputs connected to DEVCLK and Reference clock.
SLAU640A – APRIL 2019 – REVISED JUNE 2021
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CAUTION
Note
Figure 3-2
TSW14J57EVM user's guide
Copyright © 2021 Texas Instruments Incorporated
Setup Procedure
for specific instructions.
ADCxxDJxx00RF Evaluation Module
7
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