Ext Ref To Adc Pll; Onboard 50M Ref To Adc Pll System Block Diagram; Ext Ref To Adc Pll System Block Diagram - Texas Instruments TSW12QJ1600 User Manual

Customizing the EVM for Optional Clocking Support
50MHz
VCXO
Figure B-1. Onboard 50M Ref to ADC PLL System Block Diagram
B.2.2 "Ext Ref to ADC PLL"
The reference signal for the ADC PLL is provided externally from External signal generator on SMP
labeled EXT CLK(J2) . The sampling clock is generate by ADC PLL, from this external provided PLL
reference signal. In this clocking mode ADC also generate the reference clock signal for FPGA. FPGA
takes this reference clock and generates the SYSREF signal for the ADC and feed it back to the ADC.
Figure B-2 shows the block diagram of Ext Ref to ADC PLL clocking option:
• Remove R231, and populate C27.
50MHz
VCXO
J2
EXT CLK
(50-500MHz)
20
HSDC Pro Settings for Optional ADC Device Configuration
TSW12QJ1600
SE_CLK
SYNC
DA[15:0]
CLK
PLLREFO
TRIGOUT
SYSREF
TSW12QJ1600
SE_CLK
SYNC
DA[15:0]
CLK
PLLREFO
TRIGOUT
SYSREF
Figure B-2. Ext Ref to ADC PLL System Block Diagram
Copyright © 2020, Texas Instruments Incorporated
www.ti.com
FMC+
SYNC
DA[15:0]
FPGA_CLK
FPGA_GBT_CLK
ADC_SYSREF
FMC+
SYNC
DA[15:0]
FPGA_CLK
FPGA_GBT_CLK
ADC_SYSREF
SLAU796 – July 2020
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