Figure 7-3. External Reference Clocking System Block Diagram - Texas Instruments ADC DJ 00RF Series User Manual

HSDC Pro Settings for Optional ADC Device Configuration
7.2.3 External Reference Clocking Option
The Reference clock(J17) is provided by an external source. The LMK00304 make two copies of the reference
signal and sends the one copy to LMX2594 to generate the sampling clock for the ADC and LMK04828 uses
the second copy in clock distribution mode to provides the FPGA reference clock, FPGA SYSREF signal. The
ADC SYSREF signal is generated by the LMX2594.
clocking option:
The EVM can be configured to use external reference clocking option with the following steps (see
• Remove C2 and C3, populate R171 and R174
• Remove C60 and C61, populate C52 and C306
• Install Jumper J13
LMK00304
REFCLK
(J17)
260 MHz
LMK61E2
SYSREF
32.5 MHz
External
Referencel Clock

Figure 7-3. External Reference Clocking System Block Diagram

20 ADCxxDJxx00RF Evaluation Module
Figure 7-3
OSCIN
LMK04828
SDCLKx SYNC
SDCLKx SYSREFREQ
CLKIN0
SDCLKx
SDCLKx
/N
CLKIN1 DCLKx
Copyright © 2021 Texas Instruments Incorporated
shows the block diagram of external reference
ADC12DJ5200RF
LMX2594
SYNC
RFOUTA CLK
DA[15:0]
RFOUTB SYSREF
SLAU640A – APRIL 2019 – REVISED JUNE 2021
www.ti.com
Figure 7-5):
Board SYNC
FMC
SYNC
DA[15:0]
FPGA_SYSREF
FPGA_CLK[3:0]
Submit Document Feedback