Intel 8XC196NP User Manual page 300

Table 13-16. AC Timing Definitions (Continued)
Symbol
f Operating frequency
Frequency of the signal input on the XTAL1 pin times the clock multiplier ( x ). For the
8XC196NP, x is always 1; for the 80C196NU, x is 1, 2, or 4, depending on the clock mode. The
internal bus speed of the device is ½ f.
t Operating period (1/f)
All AC Timings are referenced to t.
T Address Setup to ALE Low
AVLL
Length of time ADDRESS is valid before ALE falls. Use this specification when designing the
external latch.
T Address Setup to RD# Low
AVRL
Length of time ADDRESS is valid before RD# falls.
T Address Setup to WR# Low
AVWL
Length of time ADDRESS is valid before WR# falls.
T CLKOUT High Period
CHCL
Needed in systems that use CLKOUT as clock for external devices.
T CLKOUT High to WR# Low
CHWL
Time between CLKOUT going high and WR# going active.
T CLKOUT Cycle Time
CLCL
Normally 2t.
T CLKOUT Falling to ALE Rising
CLLH
Use to derive other timings.
T ALE Cycle Time
LHLH
Minimum time between ALE pulses.
T ALE High Period
LHLL
Use this specification when designing the external latch.
T Address Hold after ALE Low
LLAX
Length of time ADDRESS is valid after ALE falls. Use this specification when designing the
external latch.
T ALE Falling to CLKOUT Rising
LLCH
Use to derive other timings.
T ALE Low to RD# Low
LLRL
Length of time after ALE falls before RD# is asserted. Could be needed to ensure proper
memory decoding takes place before a device is enabled.
T ALE Low to WR# Low
LLWL
Length of time after ALE falls before WR# is asserted. Could be needed to ensure proper
memory decoding takes place before a device is enabled.
Definition
The 8XC196N x Meets These Specifications
INTERFACING WITH EXTERNAL MEMORY
13-43