Intel 8XC196NP User Manual page 284

When selecting infinite wait states, be sure to add external hardware to count wait states and re-
lease READY within a specified period of time. Otherwise, a defective external device could tie
up the address/data bus indefinitely.
Ready control is valid only for external memory; you cannot add wait states
when accessing internal ROM.
Setup and hold timings must be met when using the READY signal to insert wait states into a bus
cycle (see Table 13-11 and Figures 13-13 through 13-15). Because a decoded, valid address is
used to generate the READY signal, the setup time is specified relative to the address being valid.
This specification, T
AVYV
and assert READY after the address is valid. The READY signal must be held valid until the
T timing specification is met. Typically, this is a minimum of 0 ns from the time CLKOUT
CLYX
goes low. Do not exceed the maximum T
might be added. In all cases, refer to the datasheets for the current specifications for T
T .
CLYX
.
Symbol
T Address Valid to Input Data Valid
AVDV
Maximum time the memory device has to output valid data after the device outputs a valid
address.
T Address Valid to READY Setup
AVYV
Maximum time the memory system has to assert READY after the device outputs the address
to guarantee that at least one wait state will occur.
T READY Hold after CLKOUT High
CHYX
If maximum specification is exceeded, additional wait states will occur.
T READY Hold after CLKOUT Low
CLYX
Minimum hold time is always 0 ns. If maximum specification is exceeded, additional wait
states will occur.
T ALE Cycle Time
LHLH
Minimum time between ALE pulses.
T RD# Low to Input Data Valid
RLDV
Maximum time the memory system has to output valid data after the device asserts RD#.
T RD# Low to RD# High
RLRH
RD# pulse width.
T Data Valid to WR# High
QVWH
Time between data being valid on the bus and WR# going inactive. Memory devices must
meet this specification.
T WR# Low to WR# High
WLWH
WR# pulse width.
NOTE
, indicates how much time the external device has to decode the address
CLYX
Table 13-11. READY Signal Timing Definitions
INTERFACING WITH EXTERNAL MEMORY
specification or additional (unwanted) wait states
Definition
and
AVYV
13-27