Intel 8XC196NP User Manual page 147

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8XC196NP, 80C196NU USER'S MANUAL
Port Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
Table 7-3 lists the registers associated with the bidirectional ports. Each port has three control reg-
isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis-
ter is a status register that returns the logic level present on the pins; it can only be read. The
registers are byte-addressable and can be windowed."Bidirectional Port Considerations" on page
7-9 discusses special considerations for reading P2_REG.7.
7-2
Table 7-2. Bidirectional Port Pins
Special-function
Special-function
Signal(s)
Signal Type
EPA0
EPA1
EPA2
EPA3
T1CLK
T1DIR
T2CLK
T2DIR
TXD
RXD
EXTINT0
BREQ#
EXTINT1
HOLD#
HLDA#
CLKOUT
CS0#
CS1#
CS2#
CS3#
CS4#
CS5#
EXTINT2
EXTINT3
PWM0
PWM1
PWM2
Associated
Peripheral
I/O
EPA
I/O
EPA
I/O
EPA
I/O
EPA
I
Timer 1
I
Timer 1
I
Timer 2
I
Timer 2
O
SIO
I/O
SIO
I
Interrupts
O
Bus controller
I
Interrupts
I
Bus controller
O
Bus controller
O
Clock generator
O
Chip-select unit
O
Chip-select unit
O
Chip-select unit
O
Chip-select unit
O
Chip-select unit
O
Chip-select unit
I
Interrupts
I
Interrupts
O
PWM
O
PWM
O
PWM
I/O

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