Initializing The Pts Control Blocks - Intel 8XC196NP User Manual

INT_PEND1
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
NMI EXTINT3
Bit
Number
7:0 Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
NMI
EXTINT3
EXTINT2
OVR2_3
OVR0_1
EPA3
EPA2
EPA1
†
An overrun on the EPA capture/compare channels can generate the multiplexed
capture overrun interrupts. The EPA_MASK and EPA_PEND registers decode these
multiplexed interrupts. Write to EPA_MASK to enable the interrupt sources; read
EPA_PEND to determine which source caused the interrupt.
Figure 6-8. Interrupt Pending 1 (INT_PEND1) Register
6.6

INITIALIZING THE PTS CONTROL BLOCKS

Each PTS interrupt requires a block of data, in register RAM, called the PTS control block
(PTSCB). The PTSCB identifies which PTS microcode routine will be invoked and sets up the
specific parameters for the routine. You must set up the PTSCB for each interrupt source before
enabling the corresponding PTS interrupts.
EXTINT2 OVR2_3
Nonmaskable Interrupt
EXTINT3 pin
EXTINT2 pin
†
EPA Capture Channel 2 or 3 Overrun
†
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
STANDARD AND PTS INTERRUPTS
Reset State:
OVR0_1 EPA3
Function
Standard Vector
FF203EH
FF203CH
FF203AH
FF2038H
FF2036H
FF2034H
FF2032H
FF2030H
Address: 0012H
00H
0
EPA2 EPA1
6-17