Introduction - Texas Instruments CDCE906 User Manual

CDCE906/CDCE706 Performance Evaluation Module
This user's guide explains how to use the CDCE906/CDCE706 performance evaluation module and
provides guidelines to build a customer's own systems. The device is soldered on the board to support
performance measurements. The device is preprogrammed (Default Setting), but can be reprogrammed
via the parallel port to meet the customer application. There is another EVM with socket available for the
purpose of sample programming. The list below shows the four devices, which can be evaluated with the
CDCE906/CDCE706 Performance Evaluation Module
- CDCE706 (EEPROM, f
- CDCE906 (EEPROM, f
- CDC706 (ROM, f
- CDC906 (ROM, f
The performance of the CDCE906 and the CDCE706 is equal, but the CDCE906 has a limited output
frequency and temperature range for operating. Because of this, the CDCE706 is used on this board for
evaluation purposes. This EVM can also be used to evaluate the generic ROM versions
CDC906/CDC706, because the functionality and performance is equal to the EEPROM version
CDCE906/CDCE706, except the EEPROM functionality.
If you need assistance with this device, email: clocks_apps@list.ti.com
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Introduction

The CDCE906/CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divider
available today. Despite its small physical outlines, the CDCE906/CDCE706 is the most flexible. It has the
capability to produce an almost independent output frequency from a given input frequency.
The input frequency can be derived from a LVCMOS, a differential input clock, or a single crystal. The
appropriate input waveform can be selected via the SMBus data interface controller.
To achieve an independent output frequency the reference divider M and the feedback divider N for each
PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The
PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output
switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider
(1-to-127) and an inverting logic for each output.
The deep M/N divider ratio allows the generation of zero ppm clocks from e.g., a 27-MHz reference input
frequency.
The CDCE906/CDCE706 includes three PLLs of those one supports SSC (spread-spectrum clocking).
PLL1, PLL2, and PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppm
applications with wide divider factors.
PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a proven method to
effectively reduce the energy for the selected frequency range. The electro-magnetic interference (EMI)
will be significantly reduced. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.
Based on the PLL frequency and the divider settings, the internal loop filter components will be
automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.
SCAU016B – August 2006 – Revised August 2007
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= 300 MHz, industrial temperature range)
max
= 167 MHz, commercial temperature range)
max
= 300 MHz, industrial temperature range)
max
= 167 MHz, commercial temperature range)
max
SCAU016B – August 2006 – Revised August 2007
CDCE906/CDCE706 Performance Evaluation Module
User's Guide
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