Tutorial - Texas Instruments CDCE906 User Manual

TI Pro-Clock™
An Error is displayed, if the setup cannot be provided by the CDCE906/CDCE706
A Warning is displayed if something in the setup needs special attention from the user.
The Accept Setup button transfers the setup to the CDCE906-706 SMBus interface, where an individual
adjustment of the setup is possible. This function is blocked if an error in the setup occurs. Discard Setup
returns to the SMBus Interface without transferring the setup.
4.3

Tutorial

This section contains a step-by-step tutorial for creating a user-defined setup and programming the
CDCE906/E706. The 27-MHz crystal of the EVM is used for reference. A 64-MHz CPU clock, different
audio sample clocks for 24-kHz audio rate, a 27-MHz clock for an MPEG/AC-3 Audio Dec, and an
additional 60-MHz clock is provided. The tutorial contains instructions and comments explaining the
functionality of the software.
Step-by-step instruction:
1. Start TI Pro-Clock™.
2. Select CDCE906/E706.
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The CDCE906-706 SMBus Interface is started.
3. Select Programming Assistant in the menu bar.
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TheCDCE906-706 Programming Assistant is started.
4. Select CDCE906 Default Setting from Default Setup in the menu bar.
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All Outputs are in use. All PLLs are in bypass mode.
5. Click disable output for Y1-Y5.
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Only Y0 is in use. All PLLs are in bypass mode.
6. Set fout of Y0 to 64 MHz.
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Y0 has an output frequency of 64 MHz; PLL 1 is set up automatically.
7. Click disable output for Y1.
8. Set fout of Y1 to 9.216 MHz.
•
Y1 is set to 9.216 MHz; PLL 2 in use by Y1.
9. Click disable output for Y2.
10. Set fout of Y2 to 18.432 MHz.
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18.432 MHz is set to Y2; PLL 1 is in use by Y1 and Y2 because Y1 and Y2 are derived from the
same PLL (groups of outputs are preferred to a single output).
11. Click disable output for Y3.
12. Set fout of Y3 to 6.144 MHz.
•
Y1, Y2, and Y3 are derived by PLL 1.
13. Click disable output for Y4.
14. Set fout of Y4 to 27 MHz.
•
27 MHz is provided to Y4 by the input clock; PLL 3 is still not in use.
The 27 MHz of Y4 can be provided by a PLL if additional jitter cleaning is necessary:
1. Click disable PLL bypass at Y4.
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PLL3 now provides 27 MHz; additional jitter cleaning is possible.
2. Click disable output at Y5.
3. Set fout of Y5 to 60 MHz.
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Error message The error for fout of Y5 is not procurable! appears; this is why no PLL is left to
derive 60 MHz for Y5.
4. Set error of Y5 to 50000 ppm.
•
Y5 now provides 59.4 MHz ; the error compared to 60 MHz is 10000 ppm.
5. Click Accept Setup.
14 CDCE906/CDCE706 Performance Evaluation Module SCAU016B – August 2006 – Revised August 2007
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