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Features
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Easy-to-use evaluation module to generate low
phase noise clocks
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Easy device setup
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Rapid configuration
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Control pins configurable through jumpers
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Requires 3.3-V power supply
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Single-ended or crystal input clock reference
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Termination available for LVPECL, LVDS, and
LVCMOS output clocks
All trademarks are the property of their respective owners.
SCAU027B - March 2009 - Revised March 2011
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Low Phase Noise Clock Evaluation Module
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© 2009-2011, Texas Instruments Incorporated
SCAU027B - March 2009 - Revised March 2011
Figure 1. CDCM6100xEVM Evaluation Board
Low Phase Noise Clock Evaluation Module
User's Guide
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Summary of Contents for Texas Instruments CDCM61004
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Page 1: Table Of Contents
Termination available for LVPECL, LVDS, and LVCMOS output clocks Figure 1. CDCM6100xEVM Evaluation Board All trademarks are the property of their respective owners. SCAU027B – March 2009 – Revised March 2011 Low Phase Noise Clock Evaluation Module Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated... -
Page 2: General Description
The CDCM6100x evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCM61004 and is representative of the performance of the CDCM61001 and CDCM61002. This fully-assembled and factory-tested evaluation board allows complete validation of all device functions. -
Page 3: Operating Mode Selection
'1'. Table 2 summarizes the available prescaler divider and feedback divider values with the corresponding PFD frequency range. SCAU027B – March 2009 – Revised March 2011 Low Phase Noise Clock Evaluation Module Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated... - Page 4 Table 4. Output Buffer Options Control Inputs Output Type LVCMOS, OSC_OUT Off LVDS, OSC_OUT Off LVPECL, OSC_OUT Off LVPECL, OSC_OUT On Low Phase Noise Clock Evaluation Module SCAU027B – March 2009 – Revised March 2011 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated...
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Page 5: Output Buffer Termination
Output Buffer Examples LVPECLOutput Buffer: Jumpers J24 and J26 should be used. This connection is illustrated in Figure SCAU027B – March 2009 – Revised March 2011 Low Phase Noise Clock Evaluation Module Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated... - Page 6 An optional bypassed output (OSC_OUT) is only available if the PLL output(s) are chosen at an LVPECL signaling level. J219 is the SMA placeholder for this output. Low Phase Noise Clock Evaluation Module SCAU027B – March 2009 – Revised March 2011 Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated...
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Page 7: Schematic
Schematic www.ti.com Schematic Figure 7. CDCM6100xEVM Schematic SCAU027B – March 2009 – Revised March 2011 Low Phase Noise Clock Evaluation Module Submit Documentation Feedback © 2009–2011, Texas Instruments Incorporated... - Page 8 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
- Page 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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