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Definitions
1 Definitions
ACRONYM
2 Introduction
The DP83825 is an ultra small form factor, very low power Ethernet Physical Layer transceiver with integrated
PMD sublayers to support 10BASE-Te, 100BASE-TX Ethernet protocols. The DP83825 interfaces directly to
twisted pair media via an external transformer. The DP83825 interfaces to the MAC layer through Reduced MII
(RMII) both in Master and Slave mode. The 50 MHz clock in RMII Master mode is synchronized to MDI derived
clock to improve the jitter in the system. The DP83825EVM demonstrates all features of DP83825 and supports
10BASE-Te and 100BASE-TX Ethernet protocols.
2.1 Key Features
•
100Base-TX, 10Base-Te
•
RMII Onboard Clock
•
Output Clock
•
Onboard MSP430F5529 for easy MDIO Register Access
•
LDO and External Power Supply Options
•
Status LEDs
•
Variable I/O Voltage Range: 1.8-V and 3.3-V
•
Bootstraps for Hardware Configuration
•
100BASE-TX Data Transfer Over 150 Meters CAT5 Cable
2
DP83825 Evaluation Module
Table 1-1. Terminology
PHY
MAC
SMI
MDIO
MDC
RGMII
SFD
VDDA
VDDIO
PD
PU
MC
Copyright © 2023 Texas Instruments Incorporated
DEFINITION
Physical Layer Transceiver
Media Access Controller
Serial Management Interface
Management Data I/O
Management Data Clock
Reduced Gigabit Media Independent Interface
Start-of-Frame Detection
Analog Core Supply Rail
Digital Supply Rail
Pulldown
Pullup
Microcontroller
SNLU239A – DECEMBER 2018 – REVISED DECEMBER 2023
www.ti.com
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