ADLINK Technology SMARC NXP iMX 8M Series User Manual page 27

LEC-iMX8M plus User's Guide 1.0
4.3.3.2 MIPI CSI1 (Camera)
Name Pin # Description
CSI1_RX0+ P7 CSI1 differential input (point to point)
CSI1_RX0- P8
CSI1_RX1+ P10
CSI1_RX1- P11
CSI1_RX2+ P13
CSI1_RX2- P14
CSI1_RX3+ P16
CSI1_RX3- P17
CSI1_CK+ P3 CSI1 differential clock input (point to
CSI1_CK- P4 point)
I2C_CAM1_DAT / S2 I2C data for serial camera data
CSI1_TX- support link or differential data lane
I2C_CAM1_CK / S1 I2C clock for serial camera data
CSI1_TX+ support link or differential data lane
CAM1_PWR# / P109 Camera 0 Power Enable, active low
GPIO1 output.
CAM1_RST# / P111 Camera 0 reset, active low output
GPIO3
CAM_MCK S6 Master clock output
Page 27
I/O I/O Power
Type Level Domain
I LVDS D-PHY Runtime
/ I LVDS M-PHY
I LVDS D-PHY Runtime
I/O OD CMOS 1.8V Runtime
/ O LVDS M-
PHY
O OD CMOS 1.8V Runtime
/ O LVDS M-
PHY
O CMOS 1.8V Runtime
O CMOS 1.8V Runtime
O CMOS 1.8V Runtime
copyright © 2021 ADLINK Technology Inc.
PU / PD Comments
PU 2.2K MIPI-CSI 2.0 mode uses I2C_CAM1_DAT
MIPI-CSI 3.0 mode uses CSI1_TX-
PU 2.2K MIPI-CSI 2.0 mode uses I2C_CAM1_CK
MIPI-CSI 3.0 mode uses CSI1_TX+
CAM1_PWR# is default, GPIO1 can be enabled
through DVT
CAM1_PWR# is default, GPIO3 can be enabled
through DVT
This signal is used by both CSI0 and CSI1
SGET SMARC Rev 2.1