ADLINK Technology SMARC NXP iMX 8M Series User Manual page 22

LEC-iMX8M plus User's Guide 1.0
4.3.1.1 LVDS0/LVDS1 mode
Name Pin # Description
LVDS0_0+ S125 Primary LVDS channel differential pair
LVDS0_0- S126 data lines
LVDS0_1+ S128
LVDS0_1 - S129
LVDS0_2+ S131
LVDS0_2- S132
LVDS0_3+ S137
LVDS0_3- S138
LVDS0_CK+ S134 Primary LVDS channel differential pair
LVDS0_CK- S135 clock lines
LCD0_VDD_EN S133 Primary LVDS channel power enable,
active high
LCD0_BKLT_EN S127 Primary LVDS channel backlight enable,
active high
LCD0_BKLT_PWM S141 Primary LVDS channel brightness control
through pulse width modulation (PWM)
LVDS1_0+ S111 Secondary LVDS channel differential pair
LVDS1_0- S112 data lines
LVDS1_1+ S114
LVDS1_1 - S115
LVDS1_2+ S117
LVDS1_2- S118
LVDS1_3+ S120
LVDS1_3- S121
LVDS1_CK+ S108 Secondary LVDS channel differential pair
LVDS1_CK- S109 clock lines.
LCD1_VDD_EN S116 Secondary panel power enable, active
high
LCD1_BKLT_EN S107 Secondary panel backlight enable, active
high
Page 22
I/O Type I/O
Level
O LVDS
LCD
O LVDS
LCD
O 1.8V
CMOS
O 1.8V
CMOS
O 1.8V
CMOS
O LVDS
LCD
O LVDS
LCD
O 1.8V
CMOS
O 1.8V
CMOS
copyright © 2021 ADLINK Technology Inc.
Power PU / PD Comments
Domain
Runtime
Runtime
Runtime
Runtime
Runtime
Runtime
Runtime
Runtime
Runtime
SGET SMARC Rev 2.1