ADLINK Technology SMARC NXP iMX 8M Series User Manual
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ADLINK Technology SMARC NXP iMX 8M Series User Manual

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LEC-IMX8MP
02/01/2021

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Summary of Contents for ADLINK Technology SMARC NXP iMX 8M Series

  • Page 1 LEC-IMX8MP 02/01/2021...
  • Page 2 Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. © Copyright 2017 ADLINK Technology, Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 3 Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. Revision History Page 3 copyright © 2021 ADLINK Technology Inc.
  • Page 4 LEC-iMX8M plus User’s Guide 1.0 SGET SMARC Rev 2.1 Revision Description Date (dd/mm/yyyy) Author Preliminary engineering version updated 05/04/2020 Preliminary engineering version updated 22/01/2021 Release version 01/02/2020 1.0.1 Change HDMI_HPD to runtime and PD 1M 24/9/2021 Page 4 copyright © 2021 ADLINK Technology Inc.

  • Page 5: Table Of Contents

    SATA Ports ................................................................... 33 4.3.8 LAN ports ..................................................................34 4.3.9 SDIO ....................................................................36 4.3.10 SPI & ESPI ..................................................................37 4.3.11 SPI0 ....................................................................37 4.3.12 ESPI ....................................................................38 General Purpose I2C ................................................................39 4.4.1 GPIO....................................................................40 Page 5 copyright © 2021 ADLINK Technology Inc.
  • Page 6 SMARC pin to controller mapping ..........................................................47 5. Software Support ............................................................. 59 5.1.1 Uboot / Yocto ................................................................59 5.1.2 Ubuntu ................................................................... 59 5.1.3 Android ..................................................................59 6. Mechanical ..............................................................61 7. Thermal Solutions ............................................................ 62 Page 6 copyright © 2021 ADLINK Technology Inc.
  • Page 7 LEC-iMX8M plus User’s Guide 1.0 SGET SMARC Rev 2.1 List of Figures Figure 1 – Module function diagram ...................................................... 15 Figure 2 – Module top/botom side pin numbering ................................................. 17 Page 7 copyright © 2021 ADLINK Technology Inc.

  • Page 8: Introduction

    Carrier Boards that implement other features such as audio CODECs, touch controllers, wireless devices, etc. The modular approach allows scalability, fast time to market and upgradability while still maintaining low costs, low power and small physical size. SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html Page 8 copyright © 2021 ADLINK Technology Inc.

  • Page 9: Specifications

    Trusted Computing Group (TCG) Trusted Platform Module (TPM) Library specifications 2.0, Level 0, Revision 138 and TCG PC Client Specific TPM Platform • Specifications 1.03 Fault-tolerant firmware loader that keeps the TPM fully functional when the loading process is interrupted (self-recovery) • SP800-193 compliant for protection, detection and recovery requirements • Page 9 copyright © 2021 ADLINK Technology Inc.

  • Page 10: Video

    DSI 4 lanes at max. 1080p@60fps display output (multiplexed with LVDS signal) Camera support - Compatible with the MIPI Alliance Interface specification v2.1 - Two MIPI-CSI2 camera inputs, one 4-lane and one 2-lane Page 10 copyright © 2021 ADLINK Technology Inc.

  • Page 11: Audio

    UART1 (main Bluetooth interface) PCM ( Bluetooth audio transfer interface ) AW-CM276F has been pre-certified by Azurewave for several countries and regions, Adlink can assist in final device certification if applicable FCC ID: UAY-W8997-M1216 Page 11 copyright © 2021 ADLINK Technology Inc.

  • Page 12: Extension Busses

    5x I2C interfaces - Support for 7-bit and 10-bit address mode - Software programmable clock frequency of 100 kbit/s in Standard-mode, 400 kbit/s in the Fast-mode or 1 Mbit/s in Fast-mode Plus GPIO Page 12 copyright © 2021 ADLINK Technology Inc.

  • Page 13: System Storage

    30-pin multipurpose flat cable connector for use with optional DB-30 debug module Provides JTAG, BMC access; UART, power test points; diagnostic LEDs, Power, Reset, Boot configuration 2.10 Boot Modes eMMC and SD-Card boot modes are supported Page 13 copyright © 2021 ADLINK Technology Inc.

  • Page 14: Power

    5-90% RH operating, non-condensing 5-95% RH storage (and operating with conformal coating) Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D Page 14 copyright © 2021 ADLINK Technology Inc.

  • Page 15: Block Diagram

    I2C_CAM0 USB configuration for ER parts I2C5 I2C_CAM1 USB0 USB2.0/OTG I2C6 USB2 USB3.0 GPIO GPIO GPIO LITE No USB HUB Expander1 Expander2 Crypto Auth. PCIe ATECC608A Figure 1 – Module function diagram Page 15 copyright © 2021 ADLINK Technology Inc.

  • Page 16: Pinout And Signal Descriptions

    The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2.1. Those signals not supported on LEC-iMX8M plus are strikethrough STRIKETHROUGH P156 S156 Page 16 copyright © 2021 ADLINK Technology Inc.
  • Page 17 SATA_RX- HDA_CK / I2S2_CK GBE0_MDI2+ SATA_ACT# GBE0_LINK_ACT# GBE1_MDI3+ ESPI_CS0# / SPI1_CS0# USB5_EN_OC GBE0_MDI1- GBE1_MDI3- ESPI_CS1# / SPI1_CS1# ESPI_IO_2 GBE0_MDI1+ GBE1_CTREF ESPI_CK / SPI1_CK ESPI_IO_3 GBE0_CTREF PCIE_D_TX+ / SERDES_1_TX+ ESPI_IO_1 / SPI1_DIN ESPI_RESET# Page 17 copyright © 2021 ADLINK Technology Inc.
  • Page 18 P120 S121 LVDS1_3- / eDP1_TX3- / DSI1_D3- PCIE_A_RX+ PCIE_B_RX+ P121 I2C_PM_CK S122 LCD1_BKLT_PWM PCIE_A_RX- PCIE_B_RX- P122 I2C_PM_DAT S123 GPIO13 P123 BOOT_SEL0# S124 PCIE_A_TX+ PCIE_B_TX+ P124 BOOT_SEL1# S125 LVDS0_0+ / eDP0_TX0+ / DSI0_D0+ Page 18 copyright © 2021 ADLINK Technology Inc.
  • Page 19 P138 SER2_RTS# S139 I2C_LCD_CK P155 VDD_IN S156 BATLOW# P139 SER2_CTS# S140 I2C_LCD_DAT P156 VDD_IN S157 TEST# P140 SER3_TX S141 LCD0_BKLT_PWM S158 P141 SER3_RX S142 GPIO12 Note : DSI0 is pinshared with LVDS0 Page 19 copyright © 2021 ADLINK Technology Inc.

  • Page 20: Signal Terminology Descriptions

    1.8V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high) 3.3Vsb 3.3V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#) 1.8Vsb 1.8V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#) Page 20 copyright © 2021 ADLINK Technology Inc.

  • Page 21: Signal Description By Function

    I2C_LCD_CK I2C_LCD_CK I2C_LCD_CK S140 I2C_LCD_DAT I2C_LCD_DAT I2C_LCD_DAT Note : LVDS0/LVDS1 are standard supported on the module Note : DSI0 can be used, this will disable the LVDS0 port, DSI1 is not supported Page 21 copyright © 2021 ADLINK Technology Inc.
  • Page 22 Secondary LVDS channel differential pair O LVDS Runtime LVDS1_CK- S109 clock lines. LCD1_VDD_EN S116 Secondary panel power enable, active 1.8V Runtime high CMOS LCD1_BKLT_EN S107 Secondary panel backlight enable, active 1.8V Runtime high CMOS Page 22 copyright © 2021 ADLINK Technology Inc.
  • Page 23 Primary panel backlight enable, active high 1.8V Runtime CMOS LCD0_BKLT_PWM S141 Primary panel brightness control through pulse width 1.8V Runtime modulation (PWM) CMOS DSI0_TE S144 Primary DSI panel tearing effect signal 1.8V Runtime CMOS Page 23 copyright © 2021 ADLINK Technology Inc.

  • Page 24: Second & Third Display Interface

    DP0_LANE3- S105 HDMI_CTRL_CK DP1_AUX+ S105 DP0_AUX+ S106 HDMI_CTRL_DAT DP1_AUX- S106 DP0_AUX- P104 HDMI_HPD DP1_HPD P104 DP0_HPD P107 DP1_AUX_SEL P107 DP0_AUX_SEL Note: DisplayPort is not supported on both second and third display interface Page 24 copyright © 2021 ADLINK Technology Inc.
  • Page 25 HDMI connector. HDMI_HPD P104 HDMI Hot plug active high detection 1.8V Runtime PD 1M Module must tolerate high level in stand-by mode signal that serves as an interrupt CMOS request Page 25 copyright © 2021 ADLINK Technology Inc.

  • Page 26: Mipi Camera Support

    CAM0_RST# / P110 Camera 0 reset, active low output O CMOS 1.8V Runtime GPIO2 CAM_MCK Master clock output O CMOS 1.8V Runtime This signal is used by both CSI0 and CSI1 Page 26 copyright © 2021 ADLINK Technology Inc.
  • Page 27 Camera 0 reset, active low output O CMOS 1.8V Runtime CAM1_PWR# is default, GPIO3 can be enabled GPIO3 through DVT CAM_MCK Master clock output O CMOS 1.8V Runtime This signal is used by both CSI0 and CSI1 Page 27 copyright © 2021 ADLINK Technology Inc.

  • Page 28: I2S (Audio)

    Module Input if CPU acts in Slave Mode AUDIO_MCK Master clock output to I2S 1.8V Runtime codec(s) CMOS Note: support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification 4.3.5 USB ports Page 28 copyright © 2021 ADLINK Technology Inc.
  • Page 29 Carrier OD driver to indicate over-current situation. USB3+ USB differential data pairs for port 3 Runtime From USB HUB USB3- USB3_SSRX+ Receive signal differential pairs for USB SS Runtime USB3_SSRX- SuperSpeed on port 3 USB SS Page 29 copyright © 2021 ADLINK Technology Inc.
  • Page 30 Pulled low by Module OD driver to disable USB0 power. Pulled CMOS 3.3V low by Carrier OD driver to indicate over-current situation. Note: USB0 is directly connected to the SOC, USB1/2/3/4/5 have shared bandwidth through a HUB Page 30 copyright © 2021 ADLINK Technology Inc.

  • Page 31: Pcie Ports

    PCIE PCIE_C_RX+ Differential PCIe link C receive data pair I LVDS Runtime Series AC coupled off module PCIE_C_RX- PCIE PCIE_C_REFCK+ Differential PCIe Link C reference clock O LVDS Runtime PCIE_C_REFCK- output PCIE Page 31 copyright © 2021 ADLINK Technology Inc.
  • Page 32 Runtime PU 10k common to PCIe links A, B, C, D CMOS Note: Module provides PCIe clock generators for PCIE_A and PCIE_B so no external clock source on the carrier is needed Page 32 copyright © 2021 ADLINK Technology Inc.

  • Page 33: Sata Ports

    LEC-iMX8M plus User’s Guide 1.0 SGET SMARC Rev 2.1 4.3.7 SATA Ports This design does not support SATA ports Page 33 copyright © 2021 ADLINK Technology Inc.

  • Page 34: Lan Ports

    Center-Tap reference voltage for Carrier board Ethernet Analog 0 to Runtime magnetic (if required by the Module GBE PHY) 3.3V max GBE0_SDP IEEE 1588 Trigger Signal. For hardware implementation 3.3V Runtime of PTP (precision time protocol) CMOS Page 34 copyright © 2021 ADLINK Technology Inc.
  • Page 35 Center-Tap reference voltage for Carrier board Ethernet Analog 0 to 3.3V Runtime magnetic `(if required by the Module GBE PHY)` GBE1_SDP IEEE 1588 Trigger Signal. For hardware implementation 3.3V Runtime of PTP (precision time protocol) CMOS Page 35 copyright © 2021 ADLINK Technology Inc.

  • Page 36: Sdio

    SDIO_PWR_EN SDIO Power Enable. This signal is used to 3.3V Runtime should be driven low in STB Mode by the enable the power being supplied to a SD/MMC card CMOS module device. Page 36 copyright © 2021 ADLINK Technology Inc.

  • Page 37: Spi & Espi

    Note: SPI0 is free to use on the carrier but support only one device through CS0 SPI1 supports a CAN bus controller on the module through CS0, that leaves CS1 free for a device on the carrier Page 37 copyright © 2021 ADLINK Technology Inc.

  • Page 38: Espi

    In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI slave output (MISO). Note: On NXP i.MX8M plus parts SPI is used Page 38 copyright © 2021 ADLINK Technology Inc.

  • Page 39: General Purpose I2C

    I2C clock for serial camera data support link MIPI CSI table I2C_PM_DAT P122 Power management I2C bus DATA (SMBus for x86) Power and System Management I2C_PM_CK P121 Power management I2C bus CLK (SMBus for x86) Power and System Management Page 39 copyright © 2021 ADLINK Technology Inc.

  • Page 40: Gpio

    PU 470K on the CMOS Module GPIO12 S142 General purpose I/O pin 1.8V Runtime PU 470K on the CMOS Module GPIO13 S123 General purpose I/O pin 1.8V Runtime PU 470K on the CMOS Module Page 40 copyright © 2021 ADLINK Technology Inc.

  • Page 41: Uart

    "Clear to Send" handshake line for port 2 1.8V Runtime CMOS SER3_TX P140 Asynchronous serial data output port 3 1.8V Runtime CMOS SER3_RX P141 Asynchronous serial data input port 3 1.8V Runtime CMOS Page 41 copyright © 2021 ADLINK Technology Inc.

  • Page 42: Can Bus

    Driven by OD depended on particular module design. Carrier function(s). on Carrier Board should leave this pin floating for normal operation WDT_TIME_OUT# S145 Watch-Dog-Timer Output, low 1.8V Runtime Driven only during runtime active. CMOS Page 42 copyright © 2021 ADLINK Technology Inc.

  • Page 43: Power And System Management

    I OD 1.8V Runtime PU 4.7K Driven by OD on Carrier. float the line in in-active state. Active low, level CMOS Pulled up on module. sensitive. Should be debounced on the Module. Page 43 copyright © 2021 ADLINK Technology Inc.

  • Page 44: Db30 Multipurpose Connector

    4.4.6 DB30 Multipurpose Connector ➢ FPC Connector type : HIROSE,FH12-30S-0.5SH(55) DB30 connector brings out the following type of signals SPI0 bus JTAG to SOC Boot Select strap pins BMC programming interface Serial port Page 44 copyright © 2021 ADLINK Technology Inc.

  • Page 45: Boot Select

    SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier. Page 45 copyright © 2021 ADLINK Technology Inc.

  • Page 46: Power

    P Not defined within Signal [2 to 3.25] / 3.25V power – 3.0V nominal. May be Terminolgy Descriptions. sourced from a Carrier based Should we define a specific Lithium cell or Super Cap. rail? Page 46 copyright © 2021 ADLINK Technology Inc.

  • Page 47: Smarc Pin To Controller Mapping

    LEC-iMX8M plus User’s Guide 1.0 SGET SMARC Rev 2.1 4.5 SMARC pin to controller mapping Page 47 copyright © 2021 ADLINK Technology Inc.
  • Page 48 DP83867 LED_0 VDDIO GBE0_MDI1- Bi-Dir GBE MDI DP83867 TD_M_B VDDIO GBE0_MDI1+ Bi-Dir GBE MDI DP83867 TD_P_B VDDIO GBE0_CTREF GBE0_MDI0- Bi-Dir GBE MDI DP83867 TD_M_A VDDIO GBE0_MDI0+ Bi-Dir GBE MDI DP83867 TD_P_A VDDIO Page 48 copyright © 2021 ADLINK Technology Inc.
  • Page 49 NVCC_ECSPI ALT0 ESPI_IO_1 / SPI1_DIN SPI / 1.8V i.MX8Mplus ECSPI1_MISO NVCC_ECSPI ALT0 ESPI_IO_0 / SPI1_DO SPI / 1.8V i.MX8Mplus ECSPI1_MOSI NVCC_ECSPI ALT0 USB0+ Bi-Dir i.MX8Mplus USB1_DP USB1_VDD33 USB0- Bi-Dir i.MX8Mplus USB1_DN USB1_VDD33 Page 49 copyright © 2021 ADLINK Technology Inc.
  • Page 50 VDDDIG1p8 PCIE_A_RX+ Serial-0.1uF PCIe i.MX8Mplus PCIE2_RXN_P PCIE2_VPH PCIE_A_RX- Serial-0.1uF PCIe i.MX8Mplus PCIE2_RXN_N PCIE2_VPH PCIE_A_TX+ Serial-0.1uF PCIe i.MX8Mplus PCIE2_TXN_P PCIE2_VPH PCIE_A_TX- Serial-0.1uF PCIe i.MX8Mplus PCIE2_TXN_N PCIE2_VPH HDMI_D2+ / DP1_LANE0+ HDMI i.MX8Mplus HDMI_TX_P_LN_2 HDMI_AVDDIO Page 50 copyright © 2021 ADLINK Technology Inc.
  • Page 51 GPIO / 1.8V SX1509 P1_1 VDD_1V8 P118 GPIO10 PU-470K GPIO / 1.8V SX1509 P1_2 VDD_1V8 P119 GPIO11 PU-470K GPIO / 1.8V SX1509 P1_3 VDD_1V8 P120 P121 I2C_PM_CK PU-2k2 I2C2 i.MX8Mplus I2C2_SCL NVCC_I2C ALT0 Page 51 copyright © 2021 ADLINK Technology Inc.
  • Page 52 From Carrier board 3 ~ 5.25 V P150 VDD_IN From Carrier board 3 ~ 5.25 V P151 VDD_IN From Carrier board 3 ~ 5.25 V P152 VDD_IN From Carrier board 3 ~ 5.25 V Page 52 copyright © 2021 ADLINK Technology Inc.
  • Page 53 TD_M_C GBE1_LINK1000# GPIO / 3.3V i.MX8Mplus TD_P_C GBE1_MDI2+ Bi-Dir GBE MDI i.MX8Mplus LED_0 GBE1_MDI2- Bi-Dir GBE MDI i.MX8Mplus TD_M_B GBE1_MDI3+ Bi-Dir GBE MDI i.MX8Mplus MDI_PLUS[3] GBE1_MDI3- Bi-Dir GBE MDI i.MX8Mplus MDI_MINUS[3] Page 53 copyright © 2021 ADLINK Technology Inc.
  • Page 54 N.C. HDA_SDI / I2S2_SDIN N.C. N.C. HDA_CK / I2S2_CK N.C. N.C. SATA_ACT# N.C. N.C. USB5_EN_OC# GPIO / 3.3V USB Hub (FL5500-2F0) DS2_OVRCURR AVDD33 ESPI_IO_2 N.C. N.C. ESPI_IO_3 N.C. N.C. ESPI_RESET# N.C. N.C. Page 54 copyright © 2021 ADLINK Technology Inc.
  • Page 55 PCIE_C_TX+ / SERDES_2_TX+ N.C. N.C. PCIE_C_TX- / SERDES_2_TX- N.C. N.C. PCIE_B_REFCK+ Serial-0.1uF PCIe PI7C9X2G304EV DIF1 VDDDIG1p8 PCIE_B_REFCK- Serial-0.1uF PCIe PI7C9X2G304EV DIF1\ VDDDIG1p8 PCIE_B_RX+ Serial-0.1uF PCIe i.MX8Mplus PCIE1_RXN_P PCIE1_VPH PCIE_B_RX- Serial-0.1uF PCIe i.MX8Mplus PCIE1_RXN_N PCIE1_VPH Page 55 copyright © 2021 ADLINK Technology Inc.
  • Page 56 LVDS1_0- / eDP1_TX0- / Serial-0R LVDS i.MX8Mplus B_Y0N DSI1_D0- S113 eDP1_HPD / DSI1_TE N.C. N.C. S114 LVDS1_1+ / eDP1_TX1+ / Serial-0R LVDS i.MX8Mplus B_Y1P DSI1_D1+ S115 LVDS1_1- / eDP1_TX1- / Serial-0R LVDS i.MX8Mplus B_Y1N DSI1_D1- Page 56 copyright © 2021 ADLINK Technology Inc.
  • Page 57 GPIO1_IO13 S134 LVDS0_CK+ / eDP0_AUX+ / Serial-0R LVDS i.MX8Mplus A_CLKP DSI0_CLK+ S135 LVDS0_CK- / eDP0_AUX- / Serial-0R LVDS i.MX8Mplus A_CLKN DSI0_CLK- S136 S137 LVDS0_3+ / eDP0_TX3+ / Serial-0R LVDS i.MX8Mplus A_Y3P DSI0_D3+ Page 57 copyright © 2021 ADLINK Technology Inc.
  • Page 58 VIN_PWR_BAD# PU-10K GPIO / 1.8V +1V8SMC S151 CHARGING# PU-68K GPIO / 1.8V i.MX8Mplus SAI5_RXC NVCC_SAI5 ALT5 S152 CHARGER_PRSNT# PU-100K GPIO / 1.8V i.MX8Mplus SAI5_RXD0 NVCC_SAI5 ALT5 S153 CARRIER_STBY# GPIO / 1.8V +1V8SMC Page 58 copyright © 2021 ADLINK Technology Inc.

  • Page 59: Software Support

    Goto : https://github.com/adlink Yocto source-code and compiling instructions are available 5.1.2 Ubuntu Build instruction from source, are available on Github 5.1.3 Android Goto : https://github.com/adlink Android source-code and compiling instructions are available Page 59 copyright © 2021 ADLINK Technology Inc.
  • Page 60 LEC-iMX8M plus User’s Guide 1.0 SGET SMARC Rev 2.1 Page 60 copyright © 2021 ADLINK Technology Inc.

  • Page 61: Mechanical

    LEC-iMX8M plus User’s Guide 1.0 SGET SMARC Rev 2.1 6. Mechanical Page 61 copyright © 2021 ADLINK Technology Inc.

  • Page 62: Thermal Solutions

    SGET SMARC Rev 2.1 7. Thermal Solutions For optimum performance LEC-IMX8M has to be cooled by a passive Heatsink / Heat-spreader optionally available for ordering HTS-sIMX8MP Heatspreader for LEC-iMX8MP THS-sIMX8MP Low profile heatsink for LEC-iMX8MP Page 62 copyright © 2021 ADLINK Technology Inc.

This manual is also suitable for:

Smarc nxp lec-imx8mpSmarc nxp i.mx8m-plus quad npuSmarc nxp i.mx8m-plus quadSmarc nxp i.mx8m-plus quadliteLec-imx8m plus

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