Signal Description By Function; The First Display Interface - ADLINK Technology SMARC NXP iMX 8M Series User Manual

LEC-iMX8M plus User's Guide 1.0

4.3 Signal Description by function

4.3.1 The First Display Interface

The first display interface is a group of 30-pins that is split into a channel 0 and channel 1. The SMARC specification allows to support either dual channel
LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each or 2 eDP ports 4 lanes each. A mix of different display type such as DSI
and eDP is also permitted.
Pin # LVDS Name MIPI DSI Name
S125 LVDS0_0+ DSI0_D0+
S126 LVDS0_0- DSI0_D0-
S128 LVDS0_1+ DSI0_D1+
S129 LVDS0_1 - DSI0_D1-
S131 LVDS0_2+ DSI0_D2+
S132 LVDS0_2- DSI0_D2-
S137 LVDS0_3+ DSI0_D3+
S138 LVDS0_3- DSI0_D3-
S134 LVDS0_CK+ DSI0_CLK+
S135 LVDS0_CK- DSI0_CLK-
S133 LCD0_VDD_EN LCD0_VDD_EN
S127 LCD0_BKLT_EN LCD0_BKLT_EN
S141 LCD0_BKLT_PWM LCD0_BKLT_PWM
S144 DSI0_TE
S139 I2C_LCD_CK I2C_LCD_CK
S140 I2C_LCD_DAT I2C_LCD_DAT
Note : LVDS0/LVDS1 are standard supported on the module
Note : DSI0 can be used, this will disable the LVDS0 port, DSI1 is not supported
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Below tables show which
eDP Name
eDP0_TX0+
eDP0_TX0-
eDP0_TX1+
eDP0_TX1-
eDP0_TX2+
eDP0_TX2-
eDP0_TX3+
eDP0_TX3-
eDP0_AUX+
eDP0_AUX-
LCD0_VDD_EN
LCD0_BKLT_EN
LCD0_BKLT_PWM
eDP0_HPD
I2C_LCD_CK
I2C_LCD_DAT
copyright © 2021 ADLINK Technology Inc.
display ports are supported
Pin # LVDS Name MIPI DSI Name
S111 LVDS1_0+ DSI1_D0+
S112 LVDS1_0- DSI1_D0-
S114 LVDS1_1+ DSI1_D1+
S115 LVDS1_1 - DSI1_D1-
S117 LVDS1_2+ DSI1_D2+
S118 LVDS1_2- DSI1_D2-
S120 LVDS1_3+ DSI1_D3+
S121 LVDS1_3- DSI1_D3-
S108 LVDS1_CK+ DSI1_CLK+
S109 LVDS1_CK- DSI1_CLK-
S116 LCD1_VDD_EN LCD1_VDD_EN
S107 LCD1_BKLT_EN LCD1_BKLT_EN
S122 LCD1_BKLT_PWM LCD1_BKLT_PWM
S113 DSI1_TE
SGET SMARC Rev 2.1
on this particular module
eDP Name
eDP1_TX0+
eDP1_TX0-
eDP1_TX1+
eDP1_TX1-
eDP1_TX2+
eDP1_TX2-
eDP1_TX3+
eDP1_TX3-
eDP1_AUX+
eDP1_AUX-
LCD1_VDD_EN
LCD1_BKLT_EN
LCD1_BKLT_PWM
eDP1_HPD