Design Principles - Quectel Smart Module Series Hardware Design

USB2_SS_RX_M
USB2_SS_RX_P
VBAT
1 μH
L1
`
GPIO
10 μF
R1
C1
10K
Figure 16: USB Type-A Interface Reference Design (USB2 for Host Mode)

3.9.3. Design Principles

Table 11: USB Trace Length Inside the Module
Pin No. Signal
J2-117 USB1_DM
J2-119 USB1_DP
J2-123 USB1_SS1_TX_M
J2-125 USB1_SS1_TX_P
J2-118 USB1_SS1_RX_M
J2-120 USB1_SS1_RX_P
J2-111 USB1_SS2_TX_M
J2-113 USB1_SS2_TX_P
J2-114 USB1_SS2_RX_M
J2-112 USB1_SS2_RX_P
SA800U-WF_Hardware_Design
USB2 3.1 channel 1
J2-100 AI
super-speed receive (-)
USB2 3.1 channel 1
J2-102 AI
super-speed receive (+)
USB2_VBUS
AW3605DNR
SW VOUT
VIN
VOUT
C2
EN
1 μF
GND
SA800U-WF Hardware Design
USB2_DP
USB2_DM
C3
USB2_SS_RX_M
C4
USB2_SS_RX_P
C5
USB2_SS_TX_M
C6
USB2_SS_TX_P
100 nF
Module
Length (mm)
39.59
39.44
22.37
23.27
19.53
20.17
19.65
19.96
15.36
14.86
Smart Module Series
USB2_VBUS
C8 C9
D1 D2 D3
4.7 μF
Length Difference (P - M)
-0.15
0.90
0.64
0.31
-0.50
52 / 106
VBUS
DP
DM
RX-
RX+
TX-
TX+
GND