Uart Interface - Quectel Smart Module Series Hardware Design

3.10. UART Interface

The module provides one debug UART used for debugging by default. The following table shows the pin
definition of debug UART interface.
Table 12: Pin Definition of Debug UART Interface
Pin Name Pin No.
DBG_TXD J2-137
DBG_RXD J2-135
Debug UART is a 2-wire UART interface of 1.8 V power domain. A level translator chip should be used if
your application is equipped with a 3.3 V UART interface. The level translator chip TXS0102DCUR
provided by Texas Instruments is recommended. The following figure shows a reference design.
VREG_S4A_1V8
DBG_TXD
DBG_RXD
The following figure is an example of connection between SA800U-WF and PC. A level translator and an
RS-232 level translator chip is recommended to be added between the module and PC, as shown below.
DBG_TXD
DBG_RXD
GND
Module
SA800U-WF_Hardware_Design
I/O
DO
DI
VCCA
C1
100 pF
OE
A1
A2
Figure 17: Reference Circuit with Level Translator Chip
1.8 V
OE
VCCA VCCB
TXD_3.3V
TXD_1.8V
RXD_1.8V RXD _3.3V
GND
TXS0102DCUR
Figure 18: RS-232 Level Match Circuit
Description
Debug UART transmit
Debug UART receive
VCCB
U1
GND
TXS0102DCUR
B1
B2
3.3 V
VCC
DIN1
DIN2
DIN3
DIN4
DIN 5
R1OUTB
ROUT1
ROUT 2
ROUT3
FORCEON
3.3 V
/FORCEOFF
SN65C3238
Smart Module Series
SA800U-WF Hardware Design
Comment
1.8 V power domain.
VDD _3.3V
C2
100 pF
TXD _3.3V
RXD _3.3 V
GND GND
DOUT1
RXD
DOUT2
DOUT3
DOUT4
DOUT5
TXD
RIN1
RIN2
RIN3
/INVALID
DB-9
54 / 106