Lvds Flat Panel Display Connector - VersaLogic Ocelot Reference Manual

Distributor of VersaLogic Corporation: Excellent Integrated System Limited
Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
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LVDS F P
LAT ANEL
The integrated LVDS flat panel display in the VL-EPMs-21 is an ANSI/TIA/EIA-644-1995
specification-compliant interface. It can support up to 24 bits of RGB pixel data plus three bits of
timing control (HSYNC/VSYNC/DE) on the four differential data output pairs. The LVDS clock
frequency ranges from 25 MHz to 112 MHz.
The +3.3V power provided to pins 19 and 20 of J6 is protected by a 1 amp fuse.
See the Connector Location Diagram on page 14 for connector location information.
VL-EPMs-21 Reference Manual
D C
ISPLAY ONNECTOR
Table 9: LVDS Flat Panel Display Pinout
J6 Signal
Pin Name
1 GND
2 NC
3 LVDSA3
4 LVDSA3#
5 GND
6 LVFSCLK0
7 LVDSCLK0#
8 GND
9 LVDSA2
10 LVDSA2#
11 GND
12 LVDSA1
13 LVDSA1#
14 GND
15 LVDSA0
16 LVDSA0#
17 GND
18 GND
19 +3.3V
20 +3.3V
Function
Ground
No Connection
Diff. Data 3 (+)
Diff. Data 3 (–)
Ground
Differential Clock (+)
Differential Clock (–)
Ground
Diff. Data 2 (+)
Diff. Data 2 (–)
Ground
Diff. Data 1 (+)
Diff. Data 1 (–)
Ground
Diff. Data 0 (+)
Diff. Data 0 (–)
Ground
Ground
Protected Power Supply
Protected Power Supply
Interfaces and Connectors
30