Table of Contents
Advertisement
Chapter 3 BIOS Configuration
Chipset Features Setup
This Setup menu controls the configuration of the Industrial CPU Card
chipset.
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
DRAM Timing
: 70ns
System BIOS Cacheable
: Disabled
Video BIOS Cacheable
: Disabled
8 Bit I/O Recovery Time
: 1
16 Bit I/O Recovery Time
: 1
Memory Hole At 15M-16M
: Disabled
PCI 2.1 Compliance
Disabled
DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower
memory.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
enabled.
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH
are cached, provided that the cache controller is enabled.
8 Bit I/O Recovery Time
This field allows you to select the recovery time allowed for 8 bit I/O. By
default, this field is set to 1 Clock.
16 Bit I/O Recovery Time
This field allows you to select the recovery time allowed for 16 bit I/O.
By default, this field is set to 1 Clock.
Memory Hole at 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory from
15MB and up unavailable to the system. Expansion cards can only access
memory up to 16MB. By default, this field is set to Disabled.
44
ROM PCI/ISA BIOS
** System Hardware Monitor *
Current CPU Temperature:
CPU Warning Temperature:
ESC : Quit
F1 : Help
PU/PD/+/- : Modify
F5 : Old Values
(Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
CI5TTV User's Manual
37°C/98°F
80°C/176°F
: Select Item
Advertisement
Table of Contents
