Sram Type; Dram Control - AOpen AP5C User Manual

SRAM Type

This parameter allows the user to select the transmission mode that
your SRAM supports. The selections are Asyn, Burst and Pipelined.
The Asyn or asynchronous mode is also known as the start-stop-bit
transmission, wherein the transmission of data is only one-way and
per character. This is the most common form of data transmission.
The Burst mode supports the simultaneous transmission of data in
fixed blocks. The Pipelined-burst mode allows simultaneous
transmission of data in four continuous clocks (no recovery time
within each clock). The default setting is

DRAM Control

Read/Write Leadoff*
Before data can be accessed, the core logic must issue the memory
address signal, the column address strobe (CAS) signal and the row
address strobe (RAS) signal to the DRAM. However, these signals
are not issued at the same time. The time difference between the
issuance of these signals is called the lead-off time.
The lead-off time for read and write actions varies depending on the
DRAM type. Some DRAMs may even require a longer delay to
access data. This parameter allows you to set the lead-off time. The
default setting is
8 T/6T
*
This parameter appears only if the Chipset Setup Mode parameter in the Advanced
Setup screen is set to Engineer
User's Guide
Asyn .
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AMI BIOS
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