Sram; Nand Flash - STMicroelectronics STM3210E-EVAL User Manual

Hardware layout and configuration
2.18
2.19
14/48
Downloaded from Elcodis.com electronic components distributor
Table 12. LCD modules (continued)
TFT LCD CN16 (default)
Pin on
Description
CN16
19 PD15
20 PD16
21 PD17
22 BL_GND
23 BL_control
24 VDD
25 VCI
26 GND
27 GND
28 BL_VDD
29 SDO
30 SDI

SRAM

512Kx16 SRAM is connected to bank1 NOR/PSRAM3 of the FSMC interface and both 8-bit
and 16-bit access are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM
respectively.

NAND Flash

The 512 Mbit x8 or 1 Gbit x8 NAND Flash is connected to bank2 of the FSMC interface. The
ready/busy signal can be connected to either WAIT signal or FSMC_INT2 signal of the
STM32F103ZGT6 depending on the setting of JP7.
Table 13. NAND Flash related jumpers
Jumper
The ready/busy signal is connected to WAIT signal when JP7 is set as
shown (default setting)
JP7
The ready/busy signal is connected to FSMC_INT2 signal when JP7 is
set as shown.
Graphic LCD U18 (optional)
Pin on
Pin connection
U18
FSMC_D13
FSMC_D14
FSMC_D15
GND
3.3V
3.3V
3.3V
GND
GND
3.3V
PA6 via JP26
PA7 via JP27
Description
Doc ID 14220 Rev 5
UM0488
Description Pin connection
1 2 3
1 2 3