Part 3.3: M.2 Interface - Alinx AXU7EV User Manual

Part 3.3: M.2 Interface

The AXU7EV FPGA development board is equipped with a PCIE x1
standard M.2 interface for connecting M.2 SSD solid state drives, with a
communication speed of up to 6Gbps. The M.2 interface uses the M key slot,
which only supports PCI-E, not SATA. When users choose SSD solid state
drives, they need to choose PCIE type SSD solid state drives.
The PCIE signal is directly connected to the BANK505 PS MGT
transceiver of ZU7EV, and the TX signal and RX signal of one channel are
connected to the LANE1 of MGT in a differential signal mode. The PCIE clock
is provided by the Si5332 chip, the frequency is 100Mhz, and the schematic
diagram of the M.2 circuit design is shown in Figure 3-2-1:
The pin assignment of M.2 interface ZYNQ is as follows:
Signal Name
PCIE_TX_N
PCIE_TX_P
PCIE_RX_N
PCIE_RX_P
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ZYNQ Ultrascale + FPGA Board AXU7EV User Manual
Figure 3-3-1: M.2 Interface Schematic
Pin Name
505_TX0_N
505_TX0_P
505_RX0_N
505_RX0_P
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Pin Number Description
PCIE Data Transmit Positive
U30
PCIE Data Transmit Negative
U29
PCIE Data Receive Positive
U34
PCIE Data Receive Negative
U33