Part 2.7: Power Supply - Alinx AXU7EV User Manual

PL System Clock Source
The core board provides a differential 200MHz PL system clock source for
the reference clock of the DDR4 controller. The crystal oscillator output is
connected to the global clock (MRCC) of PL BANK64. This global clock can be
used to drive the DDR4 controller and user logic circuits in the FPGA. The
schematic diagram of this clock source is shown in Figure 2-6-4
Clock pin assignment:

Part 2.7: Power Supply

The power supply voltage of the ACU7EV core board is DC12V, which is
supplied by connecting the carrier board. The core board uses 2
MYMGM1R824 power chips in parallel to achieve a 50A current to provide the
core power of the XCZU7EV with 0.85V. In addition, a PMIC chip TPS6508640
is used to generate all other power supplies required by the XCZU7EV chip.
For the TPS6508640 power supply design, please refer to the power supply
chip manual. The design block diagram is as follows :
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ZYNQ Ultrascale + FPGA Board AXU7EV User Manual
Figure 2-6-4: PL system clock source
Signal Name
PL_CLK0_P
PL_CLK0_N
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Pin
AJ9
AK9