Part 2.3: Ddr4 Dram - Alinx AXU7EV User Manual

 Static storage interface, support NAND, 2xQuad-SPI FLASH.
 High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode, Gigabit Ethernet
 Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
 Power management: Support the four-part division of power supply
Full/Low/PL/Battery
 Encryption algorithm: support RSA, AES and SHA.
 System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
 Logic Cells: 504K
 CLB Flip-flops: 460.8K
 Look-up-tables (LUTs): 230.4K
 Block RAM: 11Mb
 Clock Management Units (CMTs): 8
 DSP Slices: 1728
 GTH 16.3Gb/s Transceiver: 24
XCZU7EV-2FFVB1156I chip speed grade is -2, industrial grade, package
is FFVB1156.

Part 2.3: DDR4 DRAM

The ACU7EV core board is equipped with 8 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. Four DDR4
chip is mounted on the PL end, which is a 64-bit data bus width and a capacity
14 / 68
ZYNQ Ultrascale + FPGA Board AXU7EV User Manual
Amazon Store: https://www.amazon.com/alinx