Advanced Chipset Features - VIA Technologies A7F129 Manual

Mainboard User's Manual

5.4. Advanced Chipset Features

Selecting Advanced Chipset Features on the main program screen
displays this menu:
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
DRAM Timing By SPD
X DRAM Clock
X SDRAM Cycle Length
X Bank Interleave
Memory Hole
PCI Master Pipeline Req
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
Frame Buffer Size
AGP Aperture Size
AGP Mode
AGP Driving Control
X AGP Driving Value
OnChip USB
USB Keyboard Support
OnChip Sound
OnChip modem
← : MoveEnter : Select
↑ ↑ ↓ ↓ → → ←
F5:Previous Values
This screen controls the settings for the board's chipset. All entries
related to the DRAM timing on the screen are automatically config-
ured. Do not make any changes unless you are familiar with the
chipset.
DRAM Timing by SPD: Enable this item if you want the system
SPD (Serial Presence Detect) to automatically detect the speed of the
installed memory modules.
DRAM Clock: Enables the user to select the DRAM Clock. The set-
tings are 100MHz (default) and 133MHz.
SDRAM Cycle Length: This field enables you to set the CAS la-
tency time in HCLKs of 2/2 or 3/3. Do not change the values in this
field unless you change specifications of the installed DRAM or the
installed CPU.
70
Advanced Chipset Features
[Enabled]
100MHz
3
Disabled
Disabled]
[Enabled]
[Disabled]
[Disabled]
[Enabled]
[Enabled]
[16M]
[128M]
[4X]
[Auto]
DA
[Enabled]
[Disabled]
[Auto]
[Auto]
+/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F6:Fail-Safe Defaults
Figure 4 -12: Chipset features setup
Item Help
Menu Level
F7:Optimized Defaults
Advanced Chipset Features