Advanced Chipset Features - VIA Technologies A7F129 Manual

Mainboard User's Manual

4.4. Advanced Chipset Features

Selecting Advanced Chipset Features on the main program screen
displays this menu:
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
DRAM Clock
SDRAM Cycle Length
Bank Interleave
Memory Hole
PCI Master Pipeline Req
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP-4x Mode
AGP Driving Control
X AGP Driving Value
OnChip USB
USB Keyboard Support
OnChip Sound
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
← : MoveEnter : Select
↑ ↑ ↓ ↓ → → ←
F5:Previous Values
This screen controls the settings for the board's chipset. All entries
related to the DRAM timing on the screen are automatically config-
ured. Do not make any changes unless you are familiar with the
chipset.
DRAM Clock: Enables the user to select the DRAM Clock. The set-
tings are 100MHz (default) and 133MHz.
SDRAM Cycle Length: This field enables you to set the CAS la-
tency time in HCLKs of 2/2 or 3/3. Do not change the values in this
field unless you change specifications of the installed DRAM or the
installed CPU.
Bank Interleave: Enable this item to increase memory speed. When
enabled, separate memory banks are set for odd and even addresses
and the next byte of memory can be accessed while the current byte
is being refreshed. The default setting is Disabled.
42
Advanced Chipset Features
[100MHz]
[3]
[Disabled]
[Disabled]
[Enabled]
[Enabled]
[Disabled]
[Enabled]
[Enabled]
[64M]
[Enabled]
[Auto]
DA
[Enabled]
[Enabled]
[Auto]
[Enabled]
[Enabled]
[Enabled]
+/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F6:Fail-Safe Defaults
Figure 4 -4: Chipset features setup
Item Help
Menu Level
F7:Optimized Defaults
Advanced Chipset Features