VIA Technologies A7F129 Manual page 79

KM/KL Mainboard BIOS
PCI#2 Access #1 Retry: When enabled, the AGP Bus (PCI#1) ac-
cess to PCI Bus (PCI#2) is executed with the error retry feature. The
default is Enabled.
AGP Master 1 WS Write: This implements a single delay when
writing to the AGP Bus. By default, two-wait states are used by the
system, allowing for greater stability. The default is Disabled.
AGP Master 1 WS Read: This implements a single delay when
reading to the AGP Bus. By default, two-wait states are used by the
system, allowing for greater stability. The default is Disabled.
After you have made your selections in the Chipset Features Setup
screen, press <ESC> to go back to the main screen.
Advanced Chipset Features 73