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Mainboard User's Manual
2.5. CPU Packaging
Socket-462 CPUs are packaged in a PGA configuration.
2.6. Chipset
The A7F121supports VIA KT133/KT133A/KM133/KM133A/
KL133/KL133A chipsets each chipset comes in a pair—the North-
bridge chip and the Southbridge chip.
Northbridge
Southbridge
This concludes Chapter 2. Chapter 3 covers hardware installation.
12
•
CPU interface controller (266 MHz FSB)
•
AGP interface controller (AGP 4x)
•
Integrated Savage 4 2D/3D Video accelerator
KM133/133A)
•
Integrated DRAM controller
Synchronous 100/133 MHz SDRAM (KT133A)
Synchronous 66/100/133 MHz SDRAM
(KM133/KM133A/KL133/KL133A)
•
Fully synchronous PCI 2.2 bus interface
•
Data buffering:
♦
CPU-to-AGP
♦
CPU-to-DRAM
♦
CPU-to-PCI
♦
AGP-to-DRAM
♦
AGP-to-PCI
♦
PCI-to-AGP
♦
PCI-to-DRAM
•
Interface between the PCI and ISA buses
•
Power Management Logic
•
USB controller
•
EIDE controller 686A (ATA-33/66)
•
EIDE controller 686B (ATA-33/66/100)
•
Seven DMA channels
•
One timer/counter
•
Two 8-channel interrupt controllers
•
NMI logic and SMI interrupt logic
•
PCI/ISA bus arbitrator
•
SMBus interface
•
Power management Logic
•
Realtime clock (RTC)
•
ACPI controller
CPU Packaging
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